Other DataPath designs: Microprogrammed and pipelined datapaths

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Other DataPath designsMicroprogrammed and
pipelined datapaths

• Laxmikant Kale
• http//charm.cs.uiuc.edu
• Parallel Programming Laboratory
• Department of Computer Science
• University of Illinois at Urbana Champaign

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Problems with our datapath

• Other than the obvious need more registers, more
  bits in each register (and therefore in datapath)
• The clock cycle time is contrained by the longest
  possible instruction execution time.
• Solution
• break an instruction execution intoi multiple
  cycles
• Bucket brigade pipelined datapath
• Microprogrammed datapath

Access PC 1 ns
Instruction Memory 4 ns
Register read 3 ns
MUX B 1 ns
ALU or Memory 4 ns
MUX D 1 ns
Register write 3 ns
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A Microprogrammed Datapath

• The datapath we worked with for the past few
  weeks was just an example
• We will look at another datapath today
• To emphasize that alternate designs are possible
• To show an example where each instruction takes
  multiple cycles to finish
• To show a different way of generating control
  signals
• Material is not based on the book
• Used to be in the older version..
• For the exam
• Basic understanding of the slides, and
• section 8-7 (of the 3rd edition)
• Follow the weeb link there if you are interested

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Why multiple cycles?

• Wouldnt it be slower?
• Not necessarily if each clock cycle can be made
  shorter
• Variable number of cycles for instructions (some
  2, some 5)

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New Datapath

• Let us use one memory module
• for both data and instructions
• Allow for multiple cycles for each instruction

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Register File
MUX B
ALU
Memory
Data In
Address
Data Out
MUX D
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How to generate contol signals

• Consequence of this datapath
• Needs a cycle to fetch instruction from memory
• Control word
• the set of control signals
• In our older datapath
• Control word was determined fully by the
  instruction
• Here
• It depends on instruction and on which cycle
  within the instruction we are in
• Example

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Generating control sequential circuit
IR Instruction Register
Control Unit
Control word
Cycle Counter
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Generating ControlMicroprogram Memory
IR Instruction Register
Microprogram Memory
Control word
Next MicroInstruction Address
MicroProgram Counter
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Pipelined datapath

• Simplified scenario
• 4 step assembly line
• Instruction Fetch
• Operand Fetch
• Execution of operation
• Writeback
• Although total time for each instruction to
  finish is the same (or slightly larger)
• The unit as a whole processes more instructions
  per unit time
• Just as in assembly of a car
• More on this in CS 232 and beyond