ECE 425 VLSI Circuit Design

1
ECE 425 - VLSI Circuit Design

• Lecture 13 - More about Parasitics Logical
  Effort
• Spring 2005

Prof. John NestorECE DepartmentLafayette
CollegeEaston, Pennsylvania 18042nestorj_at_lafayet
te.edu
2
Announcements

• Reading
• Book 4.4-4.5, 4.7-4.8
• Verilog Handout (from ECE 313 last year) 1-4,
  5.4
• Logical Effort References
• I. Sutherland, R. Sproull, and D. Harris, Logical
  Effort Designing Fast CMOS Circuits, Morgan
  Kaufmann, 1999.
• N. Weste and D. Harris, CMOS VLSI Design, 3rd ed,
  2004.

3
Where we are

• Last Time
• Combinational Network Delay
• Today
• Effect of Diffusion Parasitics
• Logical Effort

4
Impact of Diffusion Parasitics on Delay

• The t model ignores parasitics except on output -
  is this a safe assumption?
• Consider a 2-input NAND gate -where are the
  parastics?

5
Parasitics on 2-input NAND

• How can we estimate Cpdiff and Cndiff?

6
Consider NAND Layout from Lecture 4
7
Consider NAND Layout from Lecture 4
8
Diffusion Parasitics - Summing Up
6.465fF
0.725fF
9
Diffusion Parasitics in Large Gates

• What is the effect of parasitics in a 4-input
  NAND?

10
Logical Effort - Making Sizing Systematic

• Invented by Ivan Sutherland, Sun Microsystems
• Key ideas
• Simple linear model of delay - good for hand
  calculations
• Account for loading in multiples of min-size
  inverter capacitance
• Calculate delays in terms of inverter delay t
• Account for diffusion parasitics on gate outputs
• Use to predict delay of circuits relative to each
  other instead of estimating
• Useful to set sizing from stage to stage
• Most accurate when no reconvergent fanout

11
Logical Effort - Assumptions

• Assume that µp/µn 2 (so Rp 2Rn)
• Assume all basic gates are sized for equal
  rise/fall time tr-inv tf-inv tr-nand
  tf-nand tr-nor tf-nor
• Calculate input loading of each basic gate as a
  multiple of min-size transistors gate
  capacitance
• Assume drain diffusion parasitic of a transistor
  is equal to the transistors gate capacitance

12
Transistor Sizing for LE assumptions

• What are transistor widths as a multiple of
  min-size?
• What are the input loads as a multiple of
  min-size gate cap?

2
Load 5
1
Load 4
Load 3
13
Logical Effort - Key definitions

• t - delay of a minimum-size inverter driving
  another inverter (without parasitics)
• Absolute gate delay
• dabs d t
• Values of t for common processes
• For 0.6µm process, t 50ps (approx) Sutherland
  99
• For a 180nm process, t 15ps (approx) Wester
  04
• Gate delay formula
• d f p
• Effort delay f is related to gates load.
• Parasitic delay p - due to parasitics in gate
  itself.

14
Logical Effort - Continued

• Delay formula (last slide)
• d f p
• Effort Delay
• Effort delay has two components
• f gh
• Electrical effort h is determined by gates load
• h Cout/Cin
• Logical effort g is determined by gates
  structure(see next slide)
• Modified Delay Formula
• d gh p

15
Logical Effort (g) of Common Gates

• Definition the ratio of input capacitance of the
  gate to the input capacitance of an inverter that
  can deliver the same current

16
Parasitic Delay (p) of common gates

• Assumption for one transistor diffusion
  capacitance gate capacitance
• Delay due to parasitics on min-size
  inverter Parastic loading 3C R 3RC t
• Count diffusion capacitance on output nodes only

17
Example FO4 Delay

• What is the delay of a fanout-of-4 (FO4)
  inverter?
• g1 from table - p. 14
• p1 from table - p. 15
• hCout/Cin4/14
• d gh p 14 1 5
• If t15ps in a 0.18µm technology, dabs dt
  75ps
• Note FO4 delay is often usedto characterize the
  speed of a process

From Weste Harris, CMOS VLSI Design
18
Example Ring Oscillator

• What is the frequency of an N-stage ring
  oscillator?
• g1 from table - p. 14
• p1 from table - p. 15
• hCout/Cin1/11
• d gh p 12 1 2
• Tosc 2Nd 4N fosc 1/Tosc Tosc
  1/(4N)
• Given t15ps in a 0.18µm technology, and N31
• Tosc(s) Tosct 43115ps 1.86ns
• fosc 1/Tosc 536MHz
• Ring oscillators often used as process monitors

From Weste Harris, CMOS VLSI Design
19
Example NOR Driving 10 NORs

• What is a NOR gate with input capacitance x
  driving 10 identical NOR gates?
• g 5/3 from table - p. 14
• p 4 from table - p. 15
• h Cout/Cin 10x/x 10
• d gh p 5/3 10 4 20.67
• If t15ps in a 0.18µm technology, dabs dt
  310ps
• We dont need it here, butwhat is the input
  loading x?

From Sutherland et. al., Logical Effort
20
Logical Effort along a Path

• Logical effort along a chain of gates
• G P gi
• Total electrical effort along path depends on
  ratio of first and last stage capacitance
• H Cout/Cin

g11 h1x/10
g25/3 h1y/x
g34/3 h3z/y
g41 h120/z
G g1g2g3g4 15/34/31 20/3
H 20/10 2
21
Branching Effort

• Takes into account fanout.
• Branching effort at one stage
• b (Conpath Coffpath)/ Conpath
• Branching effort along path
• B P bi

15
90
5
15
90
22
Path Delay

• Path effort
• F GBH.
• Path delay is sum of delays of gates along the
  path
• D S gi hi S pi DF P
• DF S fi
• P S pi

23
Minimizing Path Delay

• Path effort
• F GBH - independent of sizes
• Path delay is sum of delays of gates along the
  path
• D S gi hi S pi DF P
• DF S fi
• P S pi
• To minimize S fi make fi equal in each stage
• f F 1/N
• Minimum possible delay in an N-stage path
• DNF1/N P

24
Sizing the Transistors

• Optimal buffer chains are exponentially tapered
  when P0
• DNF1/N P
• Determine W/L of each gate on path by working
  backward from the last gate
• C in,i gi C out,i / f

25
Coming Up

• More About Logical Effort
• Testing

26
Logical Effort Example (Book p. 217)

• Size transistors in a chain of three two-input
  NAND gates.
• First NAND is driven by minimum-size inverter.
• Last NAND is connected to 4X inverter.
• Calculations
• Logical effort G (4/3)3
• Branching effort 1
• Electrical effort 4
• F G B H 9.5
• Optimum effort per stage f 2.1
• Output/Input Capacitance ratio of each stage

27
Another Sizing Example

• Weste Harris handout, p. 87

28
Choosing the Best Number of Stages

• Weste Harris, p. 88-90

29
Coming Up

• More about Logical Effort
• Logical Effort Examples
• Timing in ASIC Design
• Testing

30
Timing in Design Flow - Custom Layout
31
Timing in Design Flow - ASIC Design
32
Testing

• Goal of testing identify faults in hardware
• Manufacturing faults are inevitable in
  manufacturing(faults happen)
• Must identify discard faulty chips
• Types of testing
• Functional Testing - test whether circuit
  functions properly
• Performance Testing - grade ciruits based on speed

33
Testing (cont'd)

• Testing Vocabulary
• Input Vectors - values applied to device under
  test
• Output Vectors - output values in response to
  input

34
Testing Procedure

• Apply input vectors one at a time
• Examine each resulting output vector
• Compare value to "known good" value
• If different, chip is faulty
• Naïve approach to testing
• Use all possible input vectors (2n for n inputs)
• Impractical for all but very small circuits
• Alternative approach
• Model things that can go wrong in design as
  faults
• Find test vectors that expose faults
• Find shortest set of vectors that expose all
  faults

35
Fault Models - Stuck-at-0/1

• Assume that every fault forces a gate output to
  be
• Always zero - stuck-at-0
• Always one - stuck-at-1
• Testing procedure for each node in a design
• Assume that node is S-A-0
• Find a test that reveals this fault
• Assume this node is S-A-1
• Find a test that reveals this fault
• For each circuit node
• Note that one test vector may detect more than
  one fault

36
Stuck-At Faults in Gates
a b OK SA0 SA1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 0
0 1
a b OK SA0 SA1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0
0 1
NAND
NOR
37
Testing Simple Gates for Stuck-At Faults

• Assume gate output is S-A-0
• Apply a test vector that should generate a 1
• If output is 0, then gate is faulty!
• Assume gate output is S-A-1
• Apply a test vector that should generate a 0
  output
• If output is 1, then gate is faulty!

NAND Gate Test for S-A-0 with inputs 00,
01, or 10 Test for S-A-1 with inputs 11
NOR Gate Test for S-A-0 with inputs 00 Test
for S-A-1 with inputs 01, 10, or 11
38
More about Stuck-At Fault Models

• Drawback not all real faults have this behavior!
• Open circuit - may float between values
• Short circuit - may change as shorted output
  changes
• Drawback we may more than a single fault
• Even so, stuck-at fault models are used
  extensively
• Easier to work with than other models
• Shown to give good results even for non-stuck-at
  faults
• Alternative stuck-open model (see book)

39
Testing Continued

• Parts of testing
• Controlling the gate's inputs
• Observing the gate's outputs
• Example testing a S-A-0 on a node in Figure 3-44
• In industry ATPG Software used extensively

40
Testing Combinational Networks

• Goal find a short set of test vectors that will
  detect all possible stuck-at faults (100 fault
  coverage)
• Approach given a fault on a gate output
• Control the gate output to sensitize the fault by
  applying values to primary inputs
• Observe the gate output by propagating its value
  to primary outputs

41
Testing Example

• Find a test for a stuck-at-0 fault on gate D's
  output
• Justify a 1 value on w
• Justify propagation of D output value to output o1

0 if correct 1 if faulty
0
42
Redundancy

• Some circuits can't be fully tested
• Testing for S-A-0 on NOR requires making both
  inputs 0
• But this isn't possible!
• Key to the problem redundant logic
• Solution simplify to remove (ab)' b a' b'
  b a' 1 1

43
Tools for Testing

• Automatic Test Pattern Generation (ATPG)
• Searches for a test for every possible fault
• Attempts to minimize total number of vectors
• Fault Simulator
• Simulates response of faulty circuit to a set of
  test vectors
• Measures fault coverage for a given set of test
  vectors
• Design-for-Testability, Built-In Self Test
• Ways to make testing easier, especially for
  sequential circuits
• More about these later

44
Coming Up

• Sequential Logic
• Latches
• Flip-Flops
• Finite State Machines

45
Lab 7 - Verifying the DAC

• Run Magic with AMI 1.5µm technology file
• magic -T SCNA.80 cellname
• Modify RPT cell to mark resistor for extraction
• paint rpoly
• Extract circuit make Spice deck
• extract all
• exttospice cell_name
• shell spice2pspice cell_name
• Simulate using PSPICE and verify output for all
  16 input values (0000 - 1111)

46
Timing in Design Flow - Custom Layout
47
Timing in Design Flow - ASIC Design
48
Testing

• Goal of testing identify faults in hardware
• Manufacturing faults are inevitable in
  manufacturing(faults happen)
• Must identify discard faulty chips
• Types of testing
• Functional Testing - test whether circuit
  functions properly
• Performance Testing - grade ciruits based on speed

49
Testing (cont'd)

• Testing Vocabulary
• Input Vectors - values applied to device under
  test
• Output Vectors - output values in response to
  input

50
Testing Procedure

• Apply input vectors one at a time
• Examine each resulting output vector
• Compare value to "known good" value
• If different, chip is faulty
• Naïve approach to testing
• Use all possible input vectors (2n for n inputs)
• Impractical for all but very small circuits
• Alternative approach
• Model things that can go wrong in design as
  faults
• Find test vectors that expose faults
• Find shortest set of vectors that expose all
  faults

51
Fault Models - Stuck-at-0/1

• Assume that every fault forces a gate output to
  be
• Always zero - stuck-at-0
• Always one - stuck-at-1
• Testing procedure for each node in a design
• Assume that node is S-A-0
• Find a test that reveals this fault
• Assume this node is S-A-1
• Find a test that reveals this fault
• For each circuit node
• Note that one test vector may detect more than
  one fault

52
Stuck-At Faults in Gates
a b OK SA0 SA1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 0
0 1
a b OK SA0 SA1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0
0 1
NAND
NOR
53
Testing Simple Gates for Stuck-At Faults

• Assume gate output is S-A-0
• Apply a test vector that should generate a 1
• If output is 0, then gate is faulty!
• Assume gate output is S-A-1
• Apply a test vector that should generate a 0
  output
• If output is 1, then gate is faulty!

NAND Gate Test for S-A-0 with inputs 00,
01, or 10 Test for S-A-1 with inputs 11
NOR Gate Test for S-A-0 with inputs 00 Test
for S-A-1 with inputs 01, 10, or 11
54
More about Stuck-At Fault Models

• Drawback not all real faults have this behavior!
• Open circuit - may float between values
• Short circuit - may change as shorted output
  changes
• Drawback we may more than a single fault
• Even so, stuck-at fault models are used
  extensively
• Easier to work with than other models
• Shown to give good results even for non-stuck-at
  faults
• Alternative stuck-open model (see book)

55
Testing Continued

• Parts of testing
• Controlling the gate's inputs
• Observing the gate's outputs
• In industry ATPG Software used extensively

56
Testing Combinational Networks

• Goal find a short set of test vectors that will
  detect all possible stuck-at faults (100 fault
  coverage)
• Approach given a fault on a gate output
• Control the gate output to sensitize the fault by
  applying values to primary inputs
• Observe the gate output by propagating its value
  to primary outputs

57
Testing Example

• Find a test for a stuck-at-0 fault on gate D's
  output
• Justify a 1 value on w
• Justify propagation of D output value to output o1

0 if correct 1 if faulty
0
58
Redundancy

• Some circuits can't be fully tested
• Testing for S-A-0 on NOR requires making both
  inputs 0
• But this isn't possible!
• Key to the problem redundant logic
• Solution simplify to remove (ab)' b a' b'
  b a' 1 1

59
Tools for Testing

• Automatic Test Pattern Generation (ATPG)
• Searches for a test for every possible fault
• Attempts to minimize total number of vectors
• Fault Simulator
• Simulates response of faulty circuit to a set of
  test vectors
• Measures fault coverage for a given set of test
  vectors
• Design-for-Testability, Built-In Self Test
• Ways to make testing easier, especially for
  sequential circuits
• More about these later

60
Review - ASIC Design Flow
61
ASIC Design with Physical Design Tools

• Input a netlist of cells
• Design tasks
• Placement - Assign Cells to Physical Locations
• Try to keep critical nets short
• Try to ensure routability (minimize congestion)
• Try to minimize overall area
• Routing - Assign Nets to Physical Wires
• Try to keep critical nets short
• Ensure all nets routed
• Output layout

62
ASIC Design with Logic Synthesis

• Goal automate ASIC Design Process
• Translate HDL into Boolean Expressions
• Optimize design for cost and timing constraints
• Map into ASIC gate library
• History
• Two-level logic optimization algorithms - early
  1980s
• Multi-level logic optimization - mid-1980s
• Commercial logic synthesis (Synopsys) - late
  1980s
• Tighter integration with physical design - present

63
More about Logic Optimization

• Two-Level Logic Optimization
• Minimize logic in AND/OR form
• Simple Optimization Karnaugh Map
• Computer-Based Optimization
• Quine/McCluskey - Exact method (slow)
• Espresso - Heuristic method (fast)
• Multi-Level Logic Optimization
• Factor common subexpressions in a logic network
• Simplify individual nodes using two-level
  optimization
• Apply multiple transformations with command
  scripts
• Integrate with timing analysis, technology mapping

64
Outline - Introduction to Verilog

• Goals of HDL-Based Design
• Verilog Background
• A First Example
• Module and Port Declarations
• Modeling with Continuous Assignments
• Some Language Details
• Modeling with Hierarchy
• Modeling with always blocks (combinational logic)
• Demonstration Using Verilogger
• Discuss Project 1
• Summary

65
HDL Overview

• What is an HDL? A language for
• simulation - event driven model of execution
• synthesis - generates designs that match
  simulated behavior for a subset of the language
• Common HDLs
• Verilog HDL
• VHDL - VHSIC (Very High-Speed IC) HDL
• SystemC - C with class libraries to support
  System-Level Design and Hardware Design

66
Verilog History

• 1984 - Developed as a simulation language at
  Gateway Design Automation (now part of Cadence)
• 1987 - Synopsys introduces synthesis from Verilog
• 1990 - Cadence makes Verilog an "open standard"
  forms Open Verilog International (OVI) Consortium
• 1995 - Verilog becomes IEEE Standard 1364
• 2000 - Superlog language introduced as
  proprietary extension for system-level design
• 2001 - Extended Verilog 2001 Standard approved
  (support beginning to appear in CAD tools)

67
Verilog vs. VHDL - the language wars

• There are strong proponents of both languages
• Verilog is popular among US industrial ASIC
  designers
• VHDL is popular (mandatory) for DoD contractors
  and is used widely in Europe
• Verilog is somewhat easier to learn
• VHDL is more flexible and powerful

68
Differences - VHDL vs. Verilog

• Verilog
• Simple,built-in types
• No enumeration types(use symbolic constants)
• Built-in types used for synthesis
• No support for packages (use file inclusion
  instead)
• Case-sensitive
• Based on C
• Designed by one person
• Standardization
• Initial Proprietary
• IEEE Std. 1364-1995

• VHDL
• Complex, extensible types
• Enumeration types (e.g., state codes)
• Library types used for synthesis (std_logic)
• Support for packages, libraries
• Case-insensitive
• Based on Ada/Pascal
• Designed by committee
• Standardization
• Initial Defense Dept.
• IEEE 1076-1987 (-1993)

69
Verilog Simulators

• On Windows Machines Synapticad Verilogger
  (formerly veriwell)
• Available on PCs in DSP Electronics Labs
• OR download from class website
• OR borrow CD
• To run Programs-gtSynapticad/Verilogger Pro
• On the Sun Workstation Synopsys vcs / virsim
• vcs -RI
• On Windows NT Machines Cadence Verilog
• Installed, but havent used yet

70
Verilog module construct

• Key building block of language
• declaration - specifies a module interface
• Input output ports connections to outside world
• black box model - no details about internals
• body - specifies contents of "black box"
• behavior - what it does
• structure - how it's built from other "black
  boxes"

71
A First Example

• Full Adder
• module fulladder(a, b, cin, sum, cout)
• input a, b, cin
• output sum, cout
• assign sum a b cin
• assign cout a b a cin b cin
• endmodule

72
Comments about the First Example

• Verilog describes a circuit as a set of modules
• Each module has input and output ports
• Single bit
• Multiple bit - array syntax
• Each port can take on a digital value (0, 1, X,
  Z)during simulation
• Three main ways to specify module internals
• Continuous assignment statements - assign
• Concurrent statements - always
• Submodule instantiation (hierarchy)

73
Bitwise Operators

• Basic bitwise operators identical to C/C/Java
• module inv(a, y)
• input 30 a
• output 30 y
• assign y a
• endmodule

74
Reduction Operators

• Apply a single logic function to multiple-bit
  inputs
• module and8(a, y)
• input 70 a
• output y
• assign y a
• endmodule

75
Conditional Operators

• Like C/C/Java Conditional Operator
• module mux2(d0, d1, s, y)
• input 30 d0, d1
• input s
• output 30 y
• assign y s ? d1 d0// if s1, yd1, else
  yd0
• endmodule

76
More Operators

• Equivalent to C/C/Java Operators
• Arithmetic - /
• Comparison ! lt lt gt gt
• Shifting ltlt gtgt
• Example
• module adder(a, b, y)
• input 310 a, b
• output 310 y
• assign y a b
• endmodule
• Small expressions can create big hardware!

77
Bit Manipulation Concatenation

• is the concatenation operator
• module adder(a, b, y, cout)
• input 310 a, b
• output 310 y
• output cout
• assign cout,y a b
• endmodule

78
Bit Manipulation Replication

• n pattern replicates a pattern n times
• module signextend(a, y)
• input 150 a
• output 310 y
• assign y 16a15, a150
• endmodule

79
Internal Signals

• Declared using the wire keyword
• module fulladder(a, b, cin, s, cout)
• input a, b, cin
• output s, cout
• wire prop, gen
• assign prop a b
• assign gen a b
• assign s prop cin
• assign cout gen (cin prop)
• endmodule

80
Some Language Details

• Syntax - See Quick Reference Card
• Major elements of language
• Lexical Elements (tokens and token
  separators)
• Data Types and Values
• Operators and Precedence
• Syntax of module declarations

81
Verilog Lexical Elements

• Whitespace - ignored except as token separators
• blank spaces
• tabs
• newlines
• Comments
• Single-line comments //
• Multi-line comments / /
• Operators- unary, binary, ternary
• Unary a b
• Binary a b c
• Ternary a (b lt c) ? b c

82
Verilog Numbers

• Sized numbers ltsizegt'ltbase formatgtltnumbergt
• ltsizegt - decimal number specifying number of bits
• ltbase formatgt - base of number
• decimal 'd or 'D
• hex 'h or 'H
• binary b or B
• ltnumbergt - consecutive digits
• normal digits 0, 1, , 9 (if appropriate for
  base)
• hex digits a, b, c, d, e, f
• x "unknown" digit
• z "high-impedance" digit
• Examples
• 4b1111 12h7af 16d255

83
Verilog Numbers (cont'd)

• Unsized numbers
• Decimal numbers appearing as constants (236, 5,
  15, etc.)
• Bitwidth is simulator-dependent (usually 32 bits)
• Negative numbers
• sized numbers '-' before size -8'd127 -3'b111
• unsized numbers '-' before first digit -233
• Underline '_' can be used as a "spacer
• 12'b00010_1010_011 is same as
  12'b000101010011

84
Verilog Strings

• Anything in quotes is a string "This is a
  string" "a / b"
• Strings must be on a single line
• Treated as a sequence of 1-byte ASCII values
• Special characters - C-like (\)

85
Verilog Identifiers

• Starting character alphabetic or '_'
• Following characters alpha, numeric, or '_'
• Examples george _paul
• "Escaped" identifiers
• start with backslash
• follow with any non-whitespace ASCII
• end with whitespace character
• Examples \212net \xyzzy \foo
• Special notes
• Identifiers are case sensitive
• Identifiers may not be reserved words

86
Verilog Reserved Words

• always and assign begin buf bufif0 bufif1 case
• casex casez cmos deassign default defparam disabl
  e edge
• else end endcase endfunction endmodule
• endprimitive endspecify endtable endtask event for
  
• force forever fork function highz0 highz1 if ifnon
  e
• initial inout input integer join large macromodule
  
• medium module nand negedge nmos nor not
• notif0 notif or output parameter pmos
• posedge primitive pull0 pull1 pulldown pullup rcmo
  s
• real realtime reg release repeat rnmos rpmos rtran
  
• rtranif0 rtranif1 scalared small specify specparam
  strong0
• strong1 supply0 supply1 table task time tran trani
  f0
• tranif1 tri tri0 tri1 triand trior trireg vectored
  
• wait wand weak0 weak1 while wire wor xnor
• xor

87
Verilog Data Types

• Nets - connections between modules
• input, output ports
• wires - internal signals
• Other types wand, wor, trior, trireg (ignore for
  now)
• Advanced Data Types (more later)
• Vectors - multiple bit wires, registers, etc.
• reg - Variables that are assigned values
• Arrays and Memories
• Parameters

88
Operators and Precedence

• Override with parentheses () when needed

89
Verilog Module Declaration

• Describes the external interface of a single
  module
• Name
• Ports - inputs and outputs
• General Syntax
•         module modulename ( port1, port2, ... )
•           port1 direction declaration
• port2 direction declaration
• reg declarations
• module body - parallel statements
•         endmodule // note no semicolon () here!

90
Verilog Body Declaration - Parallel Statements

• Parallel statements describe concurrent behavior
  (i.e., statements which execute in parallel)
• Types of Parallel Statements
• assign - used to specify simple combinational
  logic
• always - used to specify repeating behavior for
  combinational or sequential logic
• initial - used to specify startup behavior (not
  supported in synthesis, but often used in
  simulation)
• module instantiation - used for structure
• and other features well talk about later

91
Combinational Modeling with always

• Motivation
• assign statements are fine for simple functions
• More complex functions require procedural
  modeling
• Basic syntax
• always (sensitivity-list)
• statement
• or
• always (sensitivity-list)
• begin
• statement-sequence
• end

92
Sequential Statements

• Similar to statements in C, Java, etc.
• Like C/Java, statements execute sequentially
• Value assigned values must be declared as reg
• When combined with always block
• Code is activated when inputs change
• Full execution determines final value
• Storage implied if values not assigned for all
  conditions

93
Combinational Modeling with always

• Example 4-input mux behavioral model
• module mux4(d0, d1, d2, d3, s, y)
• input d0, d1, d2, d3
• input 10 s
• output y
• reg y
• always _at_(d0 or d1 or d2 or d3 or s)
• case (s)
• 2'd0 y d0
• 2'd1 y d1
• 2'd2 y d2
• 2'd3 y d3
• default y 1'bx
• endcase
• endmodule

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Modeling with Hierarchy

• Create instances of submodules
• Example Create a 4-input Mux using mux2 module
• Original mux2 module
• module mux2(d0, d1, s, y)
• input 30 d0, d1
• input s
• output 30 y
• assign y s ? d1 d0
• endmodule

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Modeling with Hierarchy

• Create instances of submodules
• Example Create a 4-input Mux using mux2 module
• module mux4(d0, d1, d2, d3, s, y)
• input 30 d0, d1, d2, d3
• input 10 s
• output 30 y
• wire 30 low, high
• mux2 lowmux(d0, d1, s0, low)
• mux2 highmux(d2, d3, s0, high)
• mux2 finalmux(low, high, s1, y)
• endmodule

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Larger Hierarchy Example

• Use full adder to create an n-bit adder
• module add8(a, b, sum, cout)
• input 70 a, b
• output 70 sum
• output cout
• wire 70 c // used for carry connections
• assign c00
• fulladder f0(a0, b0, c0, sum0, c1)
• fulladder f1(a1, b1, c1, sum1, c2)
• fulladder f2(a2, b2, c2, sum2, c3)
• fulladder f3(a3, b3, c3, sum3, c4)
• fulladder f4(a4, b4, c4, sum4, c5)
• fulladder f5(a5, b5, c5, sum5, c6)
• fulladder f6(a6, b6, c6, sum6, c7)
• fulladder f7(a7, b7, c7, sum7, cout)
• endmodule

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Hierarchical Design with Gate Primitives

• Built-In standard logic gates
• and or not xor nand nor xnor
• Using Gate Primitives
• and g1(y, a, b, c, d)
• How are the different from operators (, , ,
  etc.)?
• Operators specify function
• Gate primitives specify structure

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Gate Primitives Example

• 2-1 Multiplexer
• module mux2s(d0, d1, s, y)
• wire sbar, y0, y1
• not inv1(sbar, s)
• and and1(y0, d0, sbar)
• and and2(y1, d1, s)
• or or1(y, y0, y1)
• endmodule
• Why shouldnt we use gate primitives?
• Requires low-level implementation decisions
• Its usually better to let synthesis tools make
  these

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Lab 8 - Comb. Design with Verilog

• Prelab write out case statement by hand for
  binary decoder
• In the lab
• Type in and simulate binary decoder using
  Verilogger
• FTP to workstations synthesize using Synopsys
  tools

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Demonstration Using Verilogger

• Starting Verilogger
• Start-gtProgram Files-gtSynapticad-gtVerilogger Pro
• Key Windows
• Project Manager
• HDL Editor Windows
• Timing Diagram Window
• Creating and Simulating a Verilog file
• Editor-gtNew HDL File
• Editor-gtSave HDL File As...
• Project-gtAdd File to Project
• Simulate-gtBuild (yellow button)
• Simulate-gtRun (green play button)

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Using Verilogger

• Create new project Project-gtNew Project
• Create HDL File(s) Editor-gtNew HDL File
• Run Simulator Simulate-gtRun
• Edit timing diagram to control input stimulus /
  observe response
• Timing diagram is represented as a separate
  verilog file

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Coming Up

• Sequential Logic
• Latches
• Flip-Flops
• Finite State Machines