ECE 425 VLSI Circuit Design

1
ECE 425 - VLSI Circuit Design

• Lecture 18 - Verilog Part 2
• Spring 2007

Prof. John NestorECE DepartmentLafayette
CollegeEaston, Pennsylvania 18042nestorj_at_lafayet
te.edu
2
Announcements

• Reading
• Book 5.1-5.4
• Verilog Handout Section 5

3
Where we are

• Last Time
• Sequential Logic
• Today
• Sequential Logic in Verilog
• Finite State Machines in Verilog

4
Outline - More about Verilog

• A Little More about Combinational Logic \
• A Quick Review
• Parameterized modules
• Symbolic Constants
• Sequential Logic
• Basic Constructs
• Synchronous Asynchronous Reset
• Mixing Combinational Registered Logic
• Examples
• Finite State Machines

5
Review - Verilog Module Declaration

• Describes the external interface of a single
  module
• Name
• Ports - inputs and outputs
• General Syntax
•         module modulename ( port1, port2, ... )
•           port1 direction declaration
• port2 direction declaration
• reg declarations
• module body - parallel statements
•         endmodule // note no semicolon () here!

6
Parameterized Modules

• Parameters - define values that can change
• Declaration
• module mod1(in1, in2, out1, out2)
• parameter Ndefault-value
• input N-1 0 in1, in2
• output N-1 0 out1
• endmodule
• Instantiation
• wire 70 w, x, y
• wire z
• mod1 (8) my_mod1(w,x,y,z)

7
Parameterized Modules Example

• N-bit 2-1 multiplexer (parameterized bitwidth)
• module mux2( sel, a, b, y )
• parameter bitwidth32
• input sel
• input bitwidth-10 a, b
• output bitwidth-10 y
• assign y sel ? b a
• endmodule
• Instantiations
• mux2 (16) my16bit_mux(s, a ,b, c)
• mux2 (5) my5bit_mux(s, d, e, f)
• mux2 (32) my32bit_mux(s, g, h, i)
• mux2 myDefault32bit_mux(s, j, k, l)

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Symbolic Constants with Parameters

• Idea use parameter to name special constants
• parameter RED_ALERT 2b11
• parameter YELLOW_ALERT 2b01
• parameter GREEN_ALERT 2b00
• Dont change in module instances
• Do this to make your code more understandable
• For others reading your code
• For yourself reading your code after some time
  has passed

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Symbolic Constant Example

• 7-segment decoder from Verilog Handout (Part 1)
• module seven_seg_display_decoder(data, segments)
• input 30 data
• output 60 segments
• reg 60 segments
• // Segment abc_defg hex
  equivalent
• parameter BLANK 7b111_1111 // h7F
• parameter ZERO 7b000_0001 // h01
• parameter ONE 7b100_1111 // h4F
• parameter TWO 7b001_0010 // h12
• parameter THREE 7b000_0110 // h06
• parameter FOUR 7b100_1100 // h4C
• parameter FIVE 7b010_0100 // h24
• parameter SIX 7b010_0000 // h20
• parameter SEVEN 7b000_1111 // h0F
• parameter EIGHT 7b000_0000 // h00
• parameter NINE 7b000_0100 // h04

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Symbolic Constant Example

• 7-segment decoder from Verilog handout Part 2)
• always _at_(data)
• case (data)
• 0 segments ZERO
• 1 segments ONE
• 2 segments TWO
• 3 segments THREE
• 4 segments FOUR
• 5 segments FIVE
• 6 segments SIX
• 7 segments SEVEN
• 8 segments EIGHT
• 9 segments NINE
• default segments BLANK
• endcase
• endmodule

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Symbolic Constants using define

• Like C/C, Verilog has a preprocessor
• define - equivalent to define in C/C
• Symbolic constant definition
• define ZERO 7b0000_0001
• Symbolic constant usage preface with
• segments ZERO
• Other preprocessor directives
• ifdef
• else
• endif

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Outline - More about Verilog

• A Little More about Combinational Logic
• A Quick Review
• Parameterized modules
• Symbolic Constants
• Sequential Logic \
• Basic Constructs
• Synchronous Asynchronous Reset
• Mixing Combinational Registered Logic
• Examples
• Discuss Lab 9

13
Sequential Design in Verilog - Basic Constructs

• Describe edge-triggered behavior using
• always block withedge event
• always _at_(posedge clock-signal)
• always _at_(negedge clock-signal)
• Nonblocking assignments (lt)
• _at_always(posedge clock-signal)
• begin
• output1 lt expression1
• . . .
• output2 lt expression2
• . . .
• end

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Simple Examples Flip-Flop, Register

• module flipflop(d, clk, q)
• input d
• input clk
• output q
• reg q
• always _at_(posedge clk)
• q lt d
• endmodule
• module flop3(clk, d, q)
• input clk
• input 30 d
• output 30 q
• reg 30 q
• always _at_(posedge clk)
• q lt d
• endmodule

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Simple Example Register with Reset

• Synchronous - resets on clock edge if reset1
• module flopr(clk, reset, d, q)
• input clk
• input reset
• input 30 d
• output 30 q
• reg 30 q
• always _at_(posedge clk)
• if (reset) q lt 4b0
• else q lt d
• endmodule

16
Simple Example Register with Reset

• Asynchronous - resets immediately if reset1
• module flopr(clk, reset, d, q)
• input clk
• input reset
• input 30 d
• output 30 q
• reg 30 q
• always _at_(posedge clk or posedge reset)
• if (reset) q lt 4b0
• else q lt d
• endmodule

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Another Example Shift Register

• module shiftreg(clk, sin, q)
• input clk
• input sin
• output 30 q
• reg 30 q
• always _at_(posedge clk)
• begin
• q3 lt q2
• q2 lt q1
• q1 lt q0
• q0 lt sin
• end
• endmodule

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Another Example 4-bit Counter

• Basic Circuit
• module counter(clk, Q)
• input clk
• output 30 Q
• reg 30 Q // a signal that is assigned a
  value
• always _at_( posedge clk )
• begin
• Q lt Q 1
• end
• endmodule
• Questions How about carry?
• Putting carry in this code would register carry
• Result carry delayed one clock cycle
• Need to mix sequential combinational logic

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Combining Sequential and Combinational Outputs

• General circuit - both registered and comb.
  outputs
• Approach multiple always blocks

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Example Adding carry to 4-bit Counter

• module counter(clk, Q, carry)
• input clk
• output 30 Q
• output carry
• reg 30 Q // a signal that is assigned a
  value
• assign carry (Q 4'b1111)
• always _at_( posedge clk )
• begin
• Q lt Q 1
• end
• endmodule

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Refining the Counter Synchronous Clear

• module counter(clk, clr, Q, carry)
• input clk, clr
• output 30 Q
• output carry
• reg 30 Q // a signal that is assigned a
  value
• assign carry (Q 4'b1111)
• always _at_( posedge clk )
• begin
• if (clr) Q lt 4'd0
• else Q lt Q 1
• end
• endmodule

22
Refining the Counter Asynchronous Clear

• module counter(clk, clr, Q, carry)
• input clk, clr
• output 30 Q
• output carry
• reg 30 Q // a signal that is assigned a
  value
• assign carry (Q 4'b1111)
• always _at_( posedge clr or posedge clk )
• begin
• if (clr) Q lt 4'd0
• else Q lt Q 1
• end
• endmodule

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Lab 8 - Comb. Design with Verilog

• Prelab write out case statement by hand for
  binary decoder
• In the lab
• Type in and simulate binary decoder using
  Verilogger or Modelsim
• FTP to Linux synthesize using Synopsys tools
• FTP to Suns convert optimized logic to layout
• FTP back from Suns examine layout

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Lab 8 - Decoder Design in Verilog

• Part 1 design, simulate, and synthesize a
  decoder
• module dec2_4(d_in, d_out)
• input 10 d_in
• output 30 d_out
• reg 30 d_out
• always _at_(d_in)
• begin
• case (d_in)
• 2b00 d_out 4b0001
• default d_out 4bxxxx
• endcase
• end
• endmodule

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Lab 8 - Decoder Design in Verilog

• Part 2 add an inverted output to your decoder
• module dec2_4(d_in, d_out, d_out_b)
• input 10 d_in
• output 30 d_out, d_out_b
• reg 30 d_out, d_out_b
• always _at_(d_in)
• begin
• case (d_in)
• 2b00 d_out 4b0001
• default d_out 4bxxxx
• endcase
• end
• endmodule

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Lab 8 - Additional Tasks

• Modify decoder to intentionally create a latch
  inference and synthesize
• Create, simulate, and synthesize designs for
• Row decoder for D/A converter (include d2 input
  and complemented outputs) - compare to your hand
  layout
• 4-bit incrementer
• 4-bit adder

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Lab 9 Part 1 Extend the Counter

• Add synchronous input updown
• Count up when updown 1
• Count down when updown 0
• Add synchronous load, data input
• Load counter with 4-bit data when load 1
• Normal counting when load 0
• Simulate using Verilogger
• Synthesize with Synopsys Tools (and plot
  schematic)
• Generate layout with db2mag note cell area
• Extract counter simulate with irsim

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Lab 9 Part 2 8-bit Shift Register

• Code shift register shown below and repeat
  previous steps to simulate and synthesize.
• 10 Extra credit parameterize shift register for
  arbitrary number of bits N and synthesize for
  N12.

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Outline - More about Verilog

• A Little More about Combinational Logic
• A Quick Review
• Parameterized modules
• Symbolic Constants
• Sequential Logic
• Basic Constructs
• Synchronous Asynchronous Reset
• Mixing Combinational Registered Logic
• Examples
• Finite State Machines

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Review - Finite State Machines

• Defined in terms of
• State Register - n flip-flops
• State - one of up to 2n values
• Transitions - conditions for state changes on
  active edge of clock
• Common Representations
• State Transition Diagrams
• State Transition Tables

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Review - State Transition Diagrams

• "Bubbles" - states
• Arrows - transition edges labeled with condition
  expressions
• Example Car Alarm

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Review - State Transition Table

• Transition List - lists edges in STD
• PS Condition NS Output
• IDLE ARM' DOOR' IDLE 0
• IDLE ARMDOOR BEEP 0
• BEEP ARM WAIT 1
• BEEP ARM' IDLE 1
• WAIT ARM BEEP 0
• WAIT ARM' IDLE 0

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State Machine Design

• Traditional Approach
• Create State Diagram
• Create State Transition Table
• Assign State Codes
• Write Excitation Equations Minimize
• HDL-Based State Machine Design
• Create State Diagram (optional)
• Write HDL description of state machine
• Synthesize

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Coding FSMs in Verilog - Explicit Style

• Clocked always block - state register
• Combinational always block -
• next state logic
• output logic

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Coding FSMs in Verilog - Code Skeleton

• Part 1 - Declarations
• module fsm(inputs, outputs)
• input . . .
• input . . .
• reg . . .
• parameter NBITS-10
• S0 2'b00
• S1 2'b01
• S2 2b'10
• S3 2b'11
• reg NBITS-1 0 CURRENT_STATE
• reg NBITS-1 0 NEXT_STATE

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Coding FSMs in Verilog - Code Skeleton

• Part 2 - State Register, Logic Specification
• always _at_(posedge clk)
• begin
• CURRENT_STATE lt NEXT_STATE
• end
• always _at_(CURRENT_STATE or xin)
• begin
• case (CURRENT_STATE)
• S0 . . . determine NEXT_STATE, outputs
• S1 . . . determine NEXT_STATE, outputs
• end case
• end // always
• endmodule

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FSM Example - Car Alarm

• Part 1 - Declarations, State Register
• module car_alarm (arm, door, reset, clk, honk )
• input arm, door, reset, clk
• output honk
• reg honk
• parameter IDLE0,BEEP1,HWAIT2
• reg 10 current_state, next_state
• always _at_(posedge reset or posedge clk)
• if (reset) current_state lt IDLE
• else current_state lt next_state

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FSM Example - Car Alarm

• Part 2 - Logic Specification
• always _at_(current_state or arm or door)
• case (current_state)
• IDLE
• begin
• honk 0
• if (arm door) next_state BEEP
• else next_state IDLE
• end
• BEEP
• begin
• honk 1
• if (arm) next_state HWAIT
• else next_state IDLE
• end

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FSM Example - Car Alarm

• Part 3 - Logic Specification (contd)
• HWAIT
• begin
• honk 0
• if (arm) next_state BEEP
• else next_state IDLE
• end
• default
• begin
• honk 0
• next_state IDLE
• end
• endcase
• endmodule

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FSM Example - Verilog Handout

• Divide-by-Three Counter

reset
S0 out0
S1 out0
S1 out1
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Verilog Code - Divide by Three CounterPart 1

• module divideby3FSM(clk, reset, out)
• input clk
• input reset
• output out
• reg 10 state
• reg 10 nextstate
• parameter S0 2b00
• parameter S1 2b01
• parameter S2 2b10
• // State Register
• always _at_(posedge clk or posedge reset)
• if (reset) state lt S0
• else state lt nextstate

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Verilog Code - Divide by Three CounterPart 2

• // Next State Logic
• always _at_(state)
• case (state)
• S0 nextstate S1
• S1 nextstate S2
• S2 nextstate S0
• default nextstate S0
• endcase
• // Output Logic
• assign out (state S2)
• endmodule

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Example from Book 01 Recognizer

• See Example 5-3, p. 285
• Output 1 when input0 for 1 clock cycle, then 1

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Verilog Code - 01 Recognizer Part 1

• module recognizer (clk, reset, rin, rout)
• input clk, reset, rin
• output rout
• reg rout
• parameter 10 bit12'b00, bit22'b01
• reg 10 current_state, next_state
• always _at_(posedge clk)
• if (reset) current_state bit1
• else current_state lt next_state
• always _at_(current_state or rin)
• case (current_state)
• bit1
• begin
• rout 1'b0
• if (rin 0) next_state bit2

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Verilog Code - 01 Recognizer Part 1

• bit2
• begin
• if (rin 1'b0)
• begin
• rout 1'b0
• next_state bit2
• end
• else
• begin
• rout 1'b1
• next_state bit1
• end
• end
• default
• begin
• rout 1'b0
• next_state bit1
• end
• endcase

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Verilogger Demo Simulate Recognizer

• Download from
• http//foghorn.cadlab.lafayette.edu/ece425/example
  s/recognizer.v
• Add to project manager and simulate
• Note that its a Mealy machine (output changes
  when input changes)

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Lab 10 - Extend and Synthesize Recognizer

• Extend to recognize the string 0110
• Adapt to use negative edge-triggered clock
• Synthesize using script compile_design.scr
• cp /home/cad/compile_design.scr
• Change file / module names in compile_design.scr
• dc_shell -f compile_design.scr
• View plot logic design with design_analyzer
• Synthesize, plot magic file, and note area

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Coming Up

• Sequential Logic Timing
• Chip-Level Design
• Project Assignment