BLOCK DIAGRAM OF DRAM CONTROLLER

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BLOCK DIAGRAM OF DRAM CONTROLLER
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In broad sense DRAM has two main functions- 1.
Refreshing, and 2. Timing generator. Why
Refreshing is essential? - To recharge
inter-electrode capacitance which is leaky in
nature and it is necessary to charge
periodically before it leaks away. - Timing
generator is needed to control read and write
cycles.
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Modes of operation of DRAM
Controller - Fast Page Mode Permits a fast
access to any one of the column
locations of a given row, successive
accesses to the
same row by pulsing CAS and latching a
new column address on each
falling edge of the
CAS strobe. - Extended Data Out (EDO) mode
A variation of page mode, but
allows shorter page cycle times than
page mode because
EDO devices do not turn off their output
drivers when CAS goes
high.
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Refresh Modes to be implemented RAS- only
Refreshing - CAS is held inactive high for the
duration of refresh cycle, and the data-in and
W inputs are dont care conditions. RAS
latches the row refresh address exactly as it
does in a normal memory access. Hidden Refresh
Cycle - This mode executes refresh cycles while
valid data is maintained at the output pin.
Holding CAS active-low at the end of a read or
write cycle while RAS is brought inactive for
tRP 70 secs. Minimum (tRP precharge time)
and then low trigers the refresh cycle. It is
nothing more than a CAS before RAS cycle
started while the current access is in progress.
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State Machine Diagram
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