Testing Semiconductor Memories

1
Testing Semiconductor Memories
Cheng-Wen Wu ???

• Lab for Reliable Computing
• Dept. Electrical Engineering
• National Tsing Hua University

2
Outline

• Introduction
• RAM functional fault models and test algorithms
• RAM fault-coverage analysis
• Cocktail-March for testing word-oriented memories
• Testing multi-port RAMs
• Testing CAMs
• Testing flash memories

3
Introduction

• Memory testing is a more and more important issue
• RAMs are key components for electronic systems
• Memories represent about 30 of the semiconductor
  market
• Embedded memories are dominating the chip yield
• Memory testing is more and more difficult
• Growing density, capacity, and speed
• Emerging new architectures and technologies
• Embedded memories access, diagnostics repair,
  heterogeneity, custom design, power noise,
  scheduling, compression, etc.
• Cost drives the need for more efficient test
  methodologies
• IFA, fault modeling and simulation, test
  algorithm development and evaluation,
  diagnostics, DFT, BIST, BIRA, BISR, etc.
• Test automation is required
• Failure analysis, fault simulation, ATG, and
  diagnostics
• BIST/BIRA/BISR generation

4
Typical RAM Production Flow
Wafer
5
Scope of RAM Testing

• Parametric Test DC AC
• Reliability Screening
• Long-cycle testing
• Burn-in static dynamic BI
• Functional Test
• Device characterization
• Failure analysis
• Fault modeling
• Simple but effective (accurate realistic?)
• Test algorithm generation
• Small number of test patterns (data backgrounds)
• High fault coverage
• Short test time

6
RAM Models

• Behavior Level
• Verilog/VHDL
• Function Level
• Verilog/VHDL/Block diagram
• Normally not synthesizable
• Circuit Level
• Spice/Schematic
• Layout Level
• GDS-II/Geometry
• Who should provide the model?

7
Memory Function Model Example
8
RAM Fault Models (Static)

• Address-Decoder Fault (AF)
• No cell accessed by certain address
• Multiple cells accessed by certain address
• Certain cell not accessed by any address
• Certain cell accessed by multiple addresses
• Stuck-At Fault (SAF)
• Cell (line) SA0 or SA1
• Transition Fault (TF)
• Cell fails to transit from 0 to 1 or 1 to 0

9
RAM Fault Models (Static)

• Bridging Fault (BF)
• Short between cells
• AND type or OR type
• Stuck-Open Fault (SOF)
• Cell not accessible due to broken line
• Neighborhood Pattern Sensitive Fault (NPSF)
• Active (Dynamic) NPSF
• Passive NPSF
• Static NPSF

10
RAM Fault Models (Static)

• Coupling Fault (CF)
• State Coupling Fault (CFst)
• Coupled (victim) cell is forced to 0 or 1 if
  coupling (aggressor) cell is in given state
• Inversion Coupling Fault (CFin)
• Transition in coupling cell complements (inverts)
  coupled cell
• Idempotent Coupling Fault (CFid)
• Coupled cell is forced to 0 or 1 if coupling cell
  transits from 0 to 1 or 1 to 0

11
RAM Fault Models (Dynamic)

• Recovery Fault (RF)
• Sense Amplifier Recovery Fault (SARF)
• Sense amp saturation after reading/writing long
  run of 0 or 1
• Write Recovery Fault (WRF)
• Write followed by reading/writing at different
  location resulting in reading/writing at same
  location
• Write-after-write recovery fault
• Read-after-write recovery fault
• Results in functional faults---detected at high
  speed (e.g., GALROW/GALCOL)
• Disturb Fault (DF)
• Victim cell forced to 0 or 1 if we read or write
  aggressor cell (may be the same cell)

12
RAM Fault Models (Dynamic)

• Data Retention Fault (DRF)
• DRAM
• Refresh Fault
• Refresh-Line Stuck-At Fault
• Leakage Fault
• Sleeping Sickness---loose data in less than
  specified hold time (typically tens of ms)
• SRAM
• Leakage Fault
• Static Data Losses---defective pull-up
• Checkerboard pattern triggers max leakage
• BIST good for sync with refresh mechanism

13
Test Time Complexity (100MHz)
14
RAM Test Algorithm

• A test algorithm (or simply test) is a finite
  sequence of test elements
• A test element contains a number of memory
  operations (access commands)
• Data pattern (background) specified for the Read
  operation
• Address (sequence) specified for the Read and
  Write operations
• A march test algorithm is a finite sequence of
  march elements
• A march element is specified by an address order
  and a number of Read/Write operations

15
Classical Test Algorithms

• Zero-One Algorithm Breuer Friedman 1976
• Also known as MSCAN
• For SAF
• Solid background (pattern)
• Complexity is 4N

16
Classical Test Algorithms

• Checkerboard Algorithm
• Zero-one algorithm with checkerboard pattern
• Complexity is 4N
• For SAF and DRF

17
Classical Test Algorithms

• Galloping Pattern (GALPAT)
• Complexity is 4N2---only for characterization
• All AFs,TFs, CFs, and SAFs are located

1. Write background 0 2. For BC 0 to N-1
Complement BC For OC 0 to N-1, OC !
BC Read BC Read OC
Complement BC 3. Write background 1 4. Repeat
Step 2
18
Classical Test Algorithms

• Sliding (Galloping) Row/Column/Diagonal
• Based on GALPAT, but instead of a bit, a complete
  row, column, or diagonal is shifted
• Complexity is 4N1.5

19
Classical Test Algorithms

• Butterfly Algorithm
• Complexity is 5NlogN

1. Write background 0 2. For BC 0 to N-1
Complement BC dist 1 While dist lt
mdist / mdist lt 0.5 col/row length /
Read cell _at_ dist north from BC
Read cell _at_ dist east from BC
Read cell _at_ dist south from BC
Read cell _at_ dist west from BC
Read BC dist 2 Complement BC 3.
Write background 1 repeat Step 2
20
Classical Test Algorithms

• Moving Inversion (MOVI) Algorithm De Jonge
  Smeulders 1976
• For functional and AC parametric test
• Functional (13N) for AF, SAF, TF, and most CF
• Parametric (12NlogN) for Read access time
• 2 successive Reads _at_ 2 different addresses with
  different data for all 2-address sequences
  differing in 1 bit
• Repeat T2T5 for each address bit
• GALPAT---all 2-address sequences

21
Classical Test Algorithms

• Surround Disturb Algorithm
• Examine how the cells in a row are affected when
  complementary data are written into adjacent
  cells of neighboring rows

1. For each cellp,q / row p and column q /
Write 0 in cellp,q-1 Write 0 in
cellp,q Write 0 in cellp,q1
Write 1 in cellp-1,q Read 0 from
cellp,q1 Write 1 in cellp1,q
Read 0 from cellp,q-1 Read 0 from
cellp,q 2. Repeat Step 1 with complementary
data
22
Classical Test Algorithms

• Zero-one and checkerboard algorithms do not have
  sufficient coverage
• Other algorithms are too time-consuming for large
  RAM
• Test time is the key factor of test cost
• Complexity ranges from N2 to NlogN
• Need linear-time test algorithms with small
  constants
• March test algorithms

23
March Tests

• Zero-One (MSCAN)
• Modified Algorithmic Test Sequence (MATS) Nair,
  Thatte Abraham 1979
• OR-type address decoder fault
• AND-type address decoder fault
• MATS Abadir Reghbati 1983
• For both OR- AND-type AFs and SAF

24
March Tests

• Marching 1/0 Breuer Friedman 1976
• For AF, SAF, and TF
• MATS Goor 1991
• Also for AF, SAF, and TF
• Complete and irredundant

25
March Tests

• March X
• For AF, SAF, TF, CFin
• March C Marinescu 1982
• For AF, SAF, TF, all CFs---redundant
• March C- Goor 1991
• Also for AF, SAF, TF, all CFs---irredundant

26
March Tests

• Limitations
• Sequential faults in address decoders
• RF
• NPSF
• ?(9N-2) for 2-CF Marinescu 1982
• ?(2NlogN11N) for 3-CF Cockburn 1994
• Solutions
• Address sequence variation
• Hopping
• Pseudorandom

27
Coverage of March Tests

• Extended March C- (11N) has a 100 coverage of
  SOF

28
Testing Word-Oriented RAM

• Background bit is replaced by background word
• MATS
• Conventional method is to use logm1 different
  backgrounds for m-bit words
• m8 00000000, 01010101, 00110011, and 00001111
• Apply the test algorithm logm14 times, so
  complexity is 46N/83N

29
Cocktail-March Algorithms

• Motivation
• Repeating the same algorithm for all logm1
  backgrounds has redundancy
• Different algorithm targets different faults
• Approach
• Use multiple backgrounds in a single algorithm
  run
• Merge and forge different algorithms and
  backgrounds into a single algorithm
• Good for word-oriented memories

30
March-CW

• Algorithm
• March C- for solid background (0000)
• Then a 5N March for each of other standard
  backgrounds (0101, 0011)
• Result
• Complexity is (105logW)N, where W is word length
  and N is word count
• Test time is reduced by 39 if W4, as compared
  with extended March C-
• Improvement increases as W increases

31
Comparison (Full Coverage)
32
Testing NPSF

• NPSF test approaches
• Tiling
• Multi-background march
• Easy BIST implementation
• 5-cell neighborhood

33
NPSF Models

• Static NPSF (SNPSF)
• BC forced to a certain state due to a certain
  deleted neighborhood (DN) pattern
• Passive NPSF (PNPSF)
• BC frozen due to a certain DN pattern
• Active NPSF (ANPSF)
• BC content changes due to a change in DN pattern
• Change a transition in one DN cell, with other
  DN cells BC containing a certain pattern
• Assumptions
• Single NPSF
• Address scramble table is available
• Memory is bit-oriented
• Word-oriented memory is tested as multiple
  bit-oriented ones

34
Test Strategy

• Multi-Background March
• To generate all neighborhood patterns

Solid BG (FC lt 30)
Another BG
35
Testing PNPSF

• March 17N

36
Data Background Generation

• Data backgrounds
• BG1 all zero
• BG2 Ar0, LSB of row address
• BG3 Ar1, second bit of row address
• BG4 Ar0?Ar1

37
Testing ANPSF

• March 12N

38
Time Complexity

• 12 N/BG X 8 BG 96N
• Detects all NPSFs

39
Multi-Port Memories

• Popular architectures
• k-port (k gt 1)
• n-read-1-write
• FIFO

40
2-Port Topology
41
Inter-Port Word-Line Short
Functional test complexity O(N3)
42
Inter-Port Bit-Line Short
Functional test complexity O(N2)
43
Address Scrambling
44
Reading Neighboring Cells

• Read neighboring cells to detect inter-port
  faults rN, rS, rE, and rW

45
TAGS-PS
46
Dual-Port RAM Test
47
Compacted Dual-Port RAM Test
Time complexity 10N
48
Four-Port RAM Test
Time complexity 17N
49
Testing 6-Read-1-Write RAM
Time complexity 13N
50
Flash Memory Testing

• Testing nonvolatile memories
• Masked ROM---exhaustive pseudorandom
• PROM (OTP) EPROM---dummy row
• EEPROM flash memory---dummy row?
• Testing flash memory core is hard
• Customized core and I/O
• Isolation (accessibility)
• Reliability issues disturbances, over
  program/erase, under program/erase, data
  retention, cell endurance, etc.
• Long program/erase time

51
Flash Memory Overview

• Flash memory can be programmed and erased
  electrically
• Has the advantages of EPROM and EEPROM
• A stacked gate transistor with both the control
  gate (CG) and floating gate (FG)

Control gate
Floating gate
D
Source
Drain
n
n
G
P-Si
S
52
Flash Memory Program Erase

• Program(1 to 0) channel hot-electron (CHE)
  injection or Fowler-Nordheim (FN) electron
  tunneling
• Erase (0 to 1) FN electron tunneling
• By the entire chip or large blocks (flash
  erasure)
• Different products have different program/erase
  mechanisms

Program
Erase
53
Flash Memory Cell Types

• Stacked-gate Split-gate
  Select-gate
• Operations Read, Program, Erase (Flash Erase)
• As opposed to Read and Write in RAM

54
Programming Scheme Comparison
55
NOR-Array Structure
56
NAND-Array Structure
Select (drain)
WL 1
WL 2
WL 3
WL 4
WL 16
Select (source)
BL i
57
Disturbance Example (I)
NOR-Type Common Ground Standard (Stacked Gate)
58
Disturbance Example (II)
59
Disturbance Example (III)
60
Disturbance Example (IV)
61
Gate Program Disturb Fault (GPDF)
Conditions 1.Victim cell initial value is a
logic 1 2.Aggressor 1?0 (program) Victim
1?0 (program)
62
Gate Erase Disturb Fault (GEDF)
Conditions 1.Victim cell initial value is a
logic 0 2.Aggressor 1?0 (program) Victim
0?1 (erase)
V(H)
V(L)
V(H)
V(L)
V(Gd)
63
Drain Program Disturb Fault (DPDF)
Conditions 1.Victim cell initial value is a
logic 1 2.Aggressor 1?0 (program) Victim
1?0 (program)
V(H)

• During programming, erased cells on unselected
  rows on a bit-line that is being programmed may
  have a fairly deep depletion region formed under
  them
• Electrons entering this depletion region can be
  accelerated by the electric field and injected
  over the oxide potential barrier to adjacent
  floating gates

V(H)
V(L)
V(Gd)
64
Drain Erase Disturb Fault (DEDF)
Conditions 1.Victim cell initial value is a
logic 0 2.Aggressor 1?0 (program) Victim
0?1 (erase)
V(H)
V(L)
V(H)
V(L)
V(Gd)
65
Read Disturb Fault (RDF)
Conditions 1. Occurs on the selected cell 2.
Cell initial value is logic 1

• Soft-Program
• During the read operation,
• hot carriers can be injected
• from the channel into the FG
• even if at low gate voltages

66
Over Erase Fault (OEF)

• Flash memory erase mechanism is not self-limiting
• Threshold voltage can be low enough to turn the
  cell into a depletion-mode transistor
• Fault behavior
• An unselected cell in the same bit-line has
  excessive source-drain leakage current
• Reading that cell leads to incorrect value (like
  DEDF)
• Cannot be programmed correctly (like TF)

67
Basic RAM Faults for Flash Memory

• Address-Decoder Fault (AF)
• Stuck-At Fault (SAF)
• Transition Fault (TF)
• Stuck-Open Fault (SOF)
• Bridging Fault (BF)
• Coupling faults need not be considered!
• Replaced by disturb faults

68
Reliability Consideration

• Reliability characteristics of floating-gate ICs
  depend on
• Circuit density, circuit design, and process
  integrity
• Memory array type and cell structure
• Reliability stressing and testing must then be
  oriented toward determining the relevant failure
  rates for the particular array under consideration

69
Data Retention Fault

• Retention time the time from data storage to the
  time at which a verifiable error is detected from
  any cause
• Intrinsic retention times exceed millions of
  years in the operating temperature range
• Months at 300C
• 1 million years at 150 C
• 120 million years at 55 C
• Data Retention Fault (DRF)
• Static leakage
• Built-in data retention test circuit

70
Cell Endurance Fault

• Endurance a measure of the ability to meet
  data-sheet specifications as a function of
  accumulated program/erase cycles
• Endurance limit is a result of damage to the
  dielectric around the floating gate caused by
  electric stresses
• In many flash devices, the end of endurance is
  generally caused by hot electron trapping in the
  charge transport oxide
• Cell Endurance Fault (CEF)
• Threshold window shift due to increased
  program/erase cycles
• Built-in stress test circuit

71
Composite Failure Rate Determination

• 125C dynamic life stress
• The 125C dynamic life stress is the standard MOS
  memory continuous dynamic read in a burn-in
  chamber
• Endurance test
• The endurance test is the repeated data
  complementing of floating-gate devices, possibly
  at temperature extremes
• Extended data retention stress
• This test is constituted by a high-temperature
  bake with a charge polarity that is opposite to
  the equilibrium state on the floating gate

72
Typical Test Modes (Characterization)

• Stress (row/column)
• Reverse tunneling stress
• Punch through stress
• Tox stress
• DC stress
• Mass program
• Weak erase
• Leak (thin-oxide, bit-line, etc.)
• Cell current cell Vt
• Margin
• Etc.

73
Test Patterns

• A RAM test pattern definition includes both the
  data pattern and the address pattern
• The time to read a pattern is the same as the
  time to write a pattern
• For flash memories, however, the address and data
  pattern definitions must be segregated
• It has long write times relative to the read
  times
• Typical data patterns
• Solid, checkerboard, random, etc.
• Typical address patterns
• Address increment/decrement, address complement,
  column/diagonal galloping, etc.

74
Testing GPDF

• Flash
• Program the first column
• Read all cells except the first column
• Flash
• Program any column except the first
• Read the first column

Assume reading and programming are done
column-wise
Source Saluja, et al., Int. Conf. VLSI Design,
2000
75
Testing GEDF

• Flash
• Program all cells
• Read all cells except the last column
• Program any column except the last
• Read the last column

Assume reading and programming are done
column-wise
Source Saluja, et al., Int. Conf. VLSI Design,
2000
76
Test Coverage Previous Results
Source Saluja, et al., Int. Conf. VLSI Design,
2000
77
March-Based Flash Test March-FT

• (f) ?(r1,w0,r0) ?(r0) (f) ?(r1,w0,r0) ?(r0)

78
Test Length (Bit-Oriented)

• Notation
• F Flash time
• P Program time
• R Read time
• r row number
• c column number

79
Test Length (Word-Oriented)

• Word length w
• 2(F)2rc(P)6rc(R)log(w)2(F)rc(P)rc(R)
• Solid 0000 (1111)
• Standard 0101 (1010), 0011 (1100)
• Ex word length w 4
• 6(F) 4rc(P) 8rc(R)

solid background testing time
standard background testing time
80
Test Algorithm Generation by Simulation (TAGS)
81
Embedded Memory Testing

• Memories are one of the most universal cores
• In Alpha 21264, cache RAMs represent 2/3
  transistors and 1/3 area in StrongArm SA110,
  the embedded RAMs occupy 90 area Bhavsar,
  ITC-99
• In average SOC, memory cores will represent more
  than 90 of the chip area by 2010 ITRS 2000
• Embedded memory testing is increasingly difficult
• High bandwidth (speed and I/O data width)
• Heterogeneity and plurality
• Isolation (accessibility)
• AC test, diagnostics, and repair
• BIST is considered the best solution

82
Embedded RAM Test Support
83
RAM BIST Approaches

• Methodology
• Processor-based BIST
• Programmable
• Hardwired BIST
• Fast
• Compact
• Interface
• Serial (scan, 1149.1)
• Parallel (embedded controller hierarchical)
• Patterns (address sequence)
• March
• Pseudorandom

84
Typical RAM BIST Architecture
85
Serial March (SMarch)

• From March C-
• Serial interface
• One BIST for all (cascaded)
• One-bit read/write at a time, but one pattern per
  cycle
• Slow
• No diagnostics

Source Nadeau-Dostie et al., IEEE DT, Apr. 1990
86
Syntest MBIST

• Algorithms
• March C-
• MOVI
• March C
• Checkerboard
• Shared controller for multiple RAMs
• Synthesizable RTL code

FSM
CE OE WEB
ADR Control
A
Data Generator
D
Analyzer
Pass BistFail Finish
Q
Source Syntest
87
NTHU/GUC EDO DRAM BIST
88
DRAM Page-Mode Read-Write Cycle
89
Programmable Memory BIST (PMBIST)
90
PMBIST Architecture
91
Controller and Sequencer

• Controller
• Microprogram
• Hardwired
• Shared CPU core
• IEEE 1149.1 TAP
• Sequencer (Pattern Generator)
• Counter
• LFSR
• LUT

92
Controller
93
Sequencer
94
PMBIST Test Modes

• Scan-Test Mode
• RAM-BIST Mode
• Functional faults
• Timing faults (setup/hold times, rise/fall times,
  etc.)
• Data retention faults
• RAM-Diagnosis Mode
• RAM-BI Mode

95
PMBIST Controller Commands
96
PMBIST Control Sequence
97
BIST Area Overhead
3
Overhead
Mem size
0.3
98
Processor-Based RAM BIST
Processor
99
On-Chip Processor-Based RAM BIST

• BIST program is stored in boot ROM during design
  phase, and memory BIST is done by executing BIST
  program

100
Testing RAM Core by On-Chip CPU

• 6502 assembly program that performs March C- test
  algorithm

data background
.org 0HFF00 LDX 00 LDA 55 M0 STA 0000,X
INX CPX FF BNE M0 LDX 00 M1 LDA 0000,
X CMP 55 BNE ERROR LDA AA STA 0000,X IN
X CPX FF BNE M1 LDX 00 . . . . .
write data background to memory
read from memory
write data background to memory
101
Test Speed Consideration

• Processor-BIST speed is lower than dedicated BIST
  circuit
• Total clock cycles to implement MARCH C- is
  O(114N)

Table 1. 6502 instruction cycles
102
NTHU Processor-Programmable BIST
103
Advantages and Disadvantages

• Advantages
• Reuse of on-chip CPU core
• Might need modification
• Core March elements can be implemented in
  hardware, allowing different March algorithms to
  be executed via assembly programming
• Disadvantages
• Some address space will be occupied by PPBIST
• Area overhead

104
PPBIST Implementation
105
PPBIST Data Registers
106
PPBIST Test Procedure
CPU write data back ground CPU write start/stop
address CPU write MARCH element instruction CPU
write START instruction to wrapper
BIST core ?(R0W1)
BIST core ?(R1W0)
BIST core ?(R0W1)
BIST core ?(R1W0)
BIST core ?(W0)
BIST core ?(R0)
write error flag write faulty address write
faulty data
yes
compare error?
no
no
complete?
yes
write complete flag
CPU take over
107
PPBIST Example Using 6502

• 6502 assembly program that performs March C- test
  algorithm under the proposed BIST scheme

108
PPBIST Example

• Addresses of the registers in the BIST experiment

• March elements and the corresponding RME

109
Experimental Results

• Total test time in terms of clock cycles
• The sum of all the March elements' test time plus
  30 clock cycles
• 10N clock cycles to perform March C-
• Test time of each March element

110
Comparison of BIST Methodologies
111
RAM BIST Compiler

• Use of RAM cores is increasing.
• SRAM, DRAM, flash RAM
• Multiple cores
• RAM BIST compiler is the trend.
• BRAINS (BIST for RAM in Seconds)
• Proposed BIST Architecture
• Memory Modeling
• Command Sequence Generation
• Configuration of the Proposed BIST

112
BRAINS Outputs

• Synthesizable BIST design
• At-speed testing
• Programmable March algorithms
• Optional diagnosis support
• BISD
• Activation sequence
• Test bench
• Synthesis script

113
BIST Synthesis Flow
114
NTHU/GUC PMBIST Architecture
115
PMBIST with Scan
Source Cheng, et al., DFT00
116
Sequencer
address
Control Module
Address Generator
Sequence Generator
go
command
Command Generator
error signature
error info.
Error Handling Module
117
State Diagram of Control Module
BIST idle
BIST idle
BIST active
BIST done
BIST apply
BIST done
BIST apply
For DRAM
For SRAM
118
DRAM Page-Mode Operation
119
Memory Specification Techniques

• Memory Specifications
• I/O Specification
• Command Specification
• Task Specification
• Delay Constraint Specification
• AC Parameter Specification
• Support customized memories.

120
I/O Specification

• Four parameters
• IO_type
• IO_width
• IO_latency
• IO_packet_length
• IO_type input, output, or inout
• IO_width port width (bits), can be a constant
  or specified by user

121
I/O Specification

• IO_latency port latency

122
I/O Modeling

• IO_packet_length bits packed within a clock
  cycle for the port

123
Command Specification

• Specifies the memorys instructions

124
Task Specification

• Specifies a complete memory operation
• A task can be a single command or a sequence of
  commands.

125
Delay Constraint Specification

• Specifies the minimal time interval between any
  two tasks

126
AC Parameter Specification

• Specifies input and output delays
• Specified parameters will be inserted into the
  synthesis script.

127
Memory Specification Example

• For ZBT SRAM
• Method A
• _at_latency D 1
• _at_task write write
• Method B
• _at_latency D 0
• _at_task write pre_write, post_write
• The BIST circuit from method A is faster than the
  one from method B, but it has higher area overhead

128
Sequence Generation

• For each March element, the compiler generates
  the command sequence according to the read task,
  write task, and minimum delay between the two
  tasks
• For example
• task read A
• task write B, C
• minimum delay between read and write 10ns
• clock period 10 ns
• Then the (rw) element becomes A, nop, B, C
• One can also optimize the command sequence

129
Fast Access Mode
130
Diagnosis Support

• The BIST circuit scans out the error information
  (element, address, signature, and polarity)
  during the diagnosis mode.
• Assume address 20h stuck-at 64h

131
Multiple RAM Cores

• Controller and sequencer can be shared.

Test pattern generator
Ram Core A
sequencer
Test pattern generator
Ram Core B
controller
Ram Core C
Test pattern generator
sequencer
132
Experimental Results

• The Built-In Memory List
• DRAM
• EDO DRAM
• SDRAM
• DDR SDRAM
• SRAM
• Single-Port Synchronous SRAM
• Single-Port Asynchronous SRAM
• Two-Port Synchronous Register File
• Dual-Port Synchronous SRAM
• Micron ZBT SRAM
• BRAINS can support new memory architecture easily

133
Experimental Results
134
Experimental Results

• Four single-port SRAM BIST circuits share the
  same controller and sequencer.
• Size of the SRAM core 8K x 16

Original BIST area for single-port SRAM 1438
(gates) Total area 1438 4 5752 (gates)
Shared gate count 3350
135
Experimental Results

• 8K x 16 single-port synchronous SRAM (0.25um)
• Area
• Die size 1780.74 x 755.07 um2
• BIST area 80.1 x 583.48 um2
• Area overhead 3.4

136
Experimental Results

• 2K x 32 two-port register file (0.25um)
• Die size 1130.74 x 936.34 um2
• BIST area 77.88 x 620 um2
• Area overhead 4.5

137
Why RAM Diagnostics?

• Memory testing is more and more important
• Memories are key components
• Represent about 30 of the semiconductor market
• Dominate the chip area/yield
• Memory testing is more and more difficult
• Growing density, capacity, and speed
• Emerging new architectures technologies
• Growing need for embedded memories
• Why diagnostics?
• Yield improvement
• Repair and/or design/process debugging

138
Fault Model Subtypes
139
NTHU-FTC BIST Architecture
140
Test Mode

• In Test Mode it runs a fixed algorithm for
  production test and repair
• Only a few pins need to be controlled, and BGO
  reports the result (Go/No-Go)

141
Fault Analysis Mode

• In Fault Analysis Mode, we can apply a longer
  March algorithm for diagnosis
• FSI captures the error information of the faulty
  cells

EOP format
142
Error Catch and Analysis

• Locate the faulty cells
• Identify the fault types

143
How to Identify Fault Type?
Tester/BIST Output
RAM Circuit/Layout
144
March Dictionary
March 11N
E0
E1 E2
E3
E4 E5
E6 E7
E8 E9
E10
145
March Signature and Error Map
March Signature (Syndrome)
Error Map
146
MECA System
147
Error Analyzer
148
Fault Analysis

• Derive analysis equations from the fault
  dictionary

• Convert error maps to fault maps by the equations

149
Test Algorithm Generation

• Start from a base test generated by TAGS or
  user-specified
• Generation options reduced to read-insertions

150
Diagnostic Resolution

• Diagnostic resolution

151
Experimental Results

• Proposed diagnosis framework has been applied to
  commercial embedded SRAMs
• Results for a 16Kx8 embedded SRAM (FS80A020) are
  shown
• Tester log from Credence SC212 is examined
• Address remapping (logical to physical) is applied

152
The Total Error Bitmap
153
Fault Bitmaps
Idempotent Coupling Fault
Stuck-at 0
154
Redundancy and Repair

• Problem We keep shrinking the feature size and
  increasing the chip density and size. How do we
  maintain the yield?
• Solutions
• Fabrication
• Material, process, equipment, etc.
• Design
• Device, circuit, etc.
• Redundancy and repair
• On-line
• EDAC (extended Hamming code product code)
• Off-line
• Spare rows and/or columns

155
From BIST to BISR
BIST
BISD
BIRA
BISR

• BIST built-in self-test
• BIECA built-in error catch analysis
• BISD built-in self diagnosis
• BIRA built-in redundancy analysis
• BISR built-in self-repair

156
RAM Built-In Self-Repair (BISR)
157
RAM Redundancy

• 1-D spare rows (or columns) only
• SRAM
• Algorithm Must-Repair
• 2-D spare rows and columns
• Local and/or global spares
• NP-complete problem
• Conventional algorithm
• Must-Repair phase
• Final-Repair phase
• Repair-Most (greedy) Tarr et al., 1984
• Fault-Driven (exhaustive, slow) Day, 1985
• Fault-Line Covering (bb) Huang et al., 1990

158
Redundancy Architectures
159
An SRAM with BISR
Kim et al., ITC 98
160
A DRAM Redundancy Example
161
Definitions

• Faulty line row or column with at least one
  faulty cell.
• A faulty line is covered if all faulty cells in
  the line are repaired by spare rows and/or
  columns.
• A faulty cell not sharing any row or column with
  any other faulty cell is an orthogonal faulty
  cell.
• r number of (available) spare rows
• c number of (available) spare columns
• F number of faulty cells in a block
• Fnumber of orthogonal faulty cells in a block

162
Example Block with Faulty Cells
163
Repair-Most (RM)

• Run BIST and construct bitmap.
• Construct row and column error counters.
• Run Must-Repair algorithm.
• Run greedy Final-Repair algorithm.

164
Worst-Case Bitmap (After Must-Repair)

• Max F2rc.

• Max Frc.

• Bitmap size (rcc)(crr).

165
Local Repair-Most (LRM)

• RM is not good enough for embedded RAM.
• Large storage requirement bitmap and counters
• Slow
• LRM improves the performance.
• Repair-Most based
• Improved heuristics
• Early termination rules
• Concurrent BIST and BIRA
• No separate Must-Repair phase
• LRM reduces the storage required.
• Smaller local bitmap
• From (rcc)x(crr) to mxn

166
LRM Algorithm

• Activated by BIST whenever a faulty cell is
  detected.
• Fault Collection (FC)
• Collects faulty-cell addresses.
• Constructs local bitmap.
• Counts row and column errors.
• Spare Allocation (SA)
• Allocate spare rows or columns when bitmap is
  full.
• Allocate spare rows or columns at end.

167
LRM FC and SA
168
LRM Example
(5,2)
(5,4),(5,6),(5,7)
(7,3)
169
Local Optimization (LO)

• LMR has drawbacks
• Selecting line with largest fault count may be
  slow.
• Multiple lines may need to be selected for
  repair.
• Area overhead is still high.
• Repair rate depends on bitmap size.
• LO has a better repair rate based on same
  hardware overhead, i.e., a higher repair
  efficiency.
• Fault Collection (FC)
• Records faulty cells in bitmap until it is full.
• Spare Allocation (SA)
• Exhaustive search performed for repairing all
  faults.
• Bitmap cleared process repeated until done.

170
LO Column/Row Selection for SA
A 1 means that the corresponding col is selected
for repair, unless empty.
Assume column selection has a lower cost than
row selection.
171
LO Example
172
Essential Spare Pivoting (ESP)

• Maintain high repair rate without using a bitmap.
• Small area overhead.
• Fault Collection (FC)
• Collect and store faulty-cell address using
  row-pivot and column-pivot registers.
• If there is a match for row (col) pivot, the
  pivot is an essential pivot.
• If there is no match, store the row/col addresses
  in the pivot registers.
• If F gt rc, the RAM is unrepairable.
• Spare Allocation (SA)
• Use row and column pivots for spare allocation.
• Spare rows (cols) for essential row (col) pivots.
• SA for orthogonal faults.

173
ESP Example
174
Cell Fault Size Distribution
Mixed Poisson-exponential distribution.
175
Repair Rate Comparison

• 1,552 RAM blocks.
• 1,024x64 bits per block.
• r from 6 to 10.
• c from 2 to 6.
• LRM bitmap rxc.
• LO bitmap 8x4.

176
Normalized Repair Rate
177
Repair Rate (r10)
178
Normalized Repair Rate (r6)
179
Area Overhead
Overhead is about 5-12 for 16Mb DRAM, r8, and
c4.
180
Computation Time (Simulated)