9. Control, memory and I/O

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9. Control, memory and I/O

• Objectives
• To define and understand the control units and
  the generation of sequences.
• To know the various types of memory.
• To understand and use the RAM
• To know the ways of reaching the peripherals of
  inputs/outputs.

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Organization of the computer...Last stage!!!
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9.1 Storage unit
Memory address registerk bits(MAR)
Memory 2k registers with N bits each one
D e c o d e r
Address
Read/ write
Data
Register of information n bits (MDR)
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Block Diagram
n lines of data input
K lines of address
Storage unit 2k registers N bits word
Read
Write
N lines of output data
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RAM (Random Access Memory)

• Random access storage, allowing reading and
  writing of information. It is often called
  read-write memory. The contents are destroyed in
  absence of power.
• 2 types
• SRAM (Static RAM)
• DRAM (Dynamic RAM)

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Types of RAM

• In addition to the SRAM and DRAM , we find
• EDORAM (Extended dated out RAM) and Burst-mode
  RAM for sequential access to the data
• Flash memory and FRAM (Ferroelectric RAM) for
  nonvolatile memory
• VRAM (Video RAM), WRAM (Window RAM), 3d RAM for
  the video memory
• SDRAM (Synchronous DRAM)
• Memory with local hiding place CDRAM (Cached
  DRAM), EDRAM (Enhanced DRAM), CVRAM (Cached VRAM)
• MEMORY GDR RAM

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9.2 Control unit
MAR
MDR
OpCode
OpAddr
A
DS
RW
PC
Control
HZN
ALU
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A) Word Time for serial operation mode

• Type of sequence necessary for the serial
  transfer between two registers. The produced
  signal corresponds to the transfer time of a word
  
• bits of required clock ticks.

1
2
3
4
5
6
7
0
C
Start
Stop
Q
Time of a word (8 bits)
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A) Word Time for serial operation mode

• Realization using a SR flip-flop and a binary
  counter.

Start
S
Q
Control signal
C
C
R
Stop
3 bits counter (with enable)
Count enable
C
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A) Word Time for serial operation mode

• Quiz What should be modified in the preceding
  diagram for a word length of
• a) 5 clock pulses
• b) 13 clock pulses
• Think about the counter and about the inputs of
  the AND gate...

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a) 5 ticks

• Realization using a SR flip-flop and a binary
  counter of modulo 5.

Start
S
Q
Control Signal
C
C
R
Stop
22
3 bits counter (modulo 5)
Count enable
C
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b) 13 ticks

• Realization using a SR flip-flop and a binary
  counter of modulo 13.

Start
S
Q
Control Signal
C
C
R
Stop
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22
4 bits Counter (modulo 13)
Count enable
C
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B) Word Time for parallel operation mode

• We see 2 different implementations.

C
T0
T1
T2
T3
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B) Word Time for parallel operation mode

• a) Realization with counter and decoder

T0 T1 T2 T3
Decoder 2 x 4
2 bits Counter
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B) Word Time for parallel operation mode

• b) Realization with circular counter (ring
  counter) composed of a circular shift register
  where, at any time, only one flip-flop has the
  logical value "1". This value is shifted with
  each clock pulse. Initially, the counter contains
  1000.

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Self-correcting counters

• The use of a counter can also lead to problems
  that certain states are unutilized. It is then
  necessary it to make it self-correcting, to
  tolerate such case. Example sequence of
  counting 0, 1, 2

?
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Self-correcting counters

• Not self-correcting. If the counter falls, by
  error, in an invalid state 3, it will remain
  there indefinitely (or until a forthcoming error).

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Self-correcting counters

• Self-correcting! The invalid state 3 leads
  (directly or indirectly) to a valid state in the
  counting sequence

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Self-correcting counters

• One can make the counters self-correcting at the
  time of their design (for example, one decides
  that state 3 will have 0 like following state).
  That can make the circuit more complex (there is
  less of X in the Karnaugh map).
• If one leaves the following state of 3
  unspecified (X) at the time of the design, that
  does not necessarily say that the circuit will
  not be self-correcting. It may be the case that
  the groupings of X make that state 3 a valid
  state (0, 1 or 2).

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9.3 Bus and circuits of I/O

• Inputs/outputs Module
• Transfer of data between the memory and the I/O
  circuits (connected to the peripherals), with or
  without the CPU intervention.
• Interface, controller and I/O processor
• Modes of transfer, DMA
• Interrupts

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Inputs/outputs Module (I)
CPU
I/O Circuit
Shared memory I/O

• Bus for control, addresses, data comm., and the
  I/O operations.
• Part of the memory addresses is used to address
  ports connected to the I/O circuit.
• There are no instructions for distinct I/O
  (load/store and read/write with the I/O).

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Inputs/outputs Module (II)
CPU
I/O Circuit
Independent memory I/O

• Bus for address and data comm., but control bus
  for the memory access is different from I/O
  operation.
• The memory addresses and the ports connected to
  the I/O circuit are independent
• There are distinct instructions for reading and
  writing with the I/O.

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Inputs/outputs Module (III)
CPU, DMA controller or I/O processor
I/O Circuit
DMA Memory

• Two sets of different bus (control, addresses,
  data), one for the memory access and the other
  for the I/O operations.
• The memory addresses and the ports connected to
  the I/O circuits are independent
• There are distinct instructions for reading and
  writing with the I/O.

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Complementary readings

• Mano and Kime
• 6.2-6.4 RAM (except Waveforms Timing)
• 7.5, 7.6, 7.9-7.11 Bus and Data
• 8.1-8.4, 8.8 Control unit
• 11.1, 11.3, 11.5, 11.7 I/O and DMA