History

1
History

• 1959 first IC's
• 1971 µP 4004 4Bit Intel (2000 Tr.)
• 1972 µP 8008 8Bit Intel (5000 Tr.)
• 1974 µP 8080 8Bit Intel (6000 Tr.)
• 1974 µP 6800 8Bit Motorola
• 1975 µP Z80 8Bit Zilog
• 1976 µP 9900 16Bit Texas Instruments
• 1978 µP 8086 16Bit Intel (50.000 Tr)
• 1982 µP 8286 16Bit Intel (100.000 Tr.)
• 1985 µP 80386 16Bit Intel (300.000 Tr.)
• 1989 µP 80486 16Bit Intel (106 Tr.)
• 1993 µP 80586 16Bit Intel (5106 Tr.)
• ...

2
Z80 Development

• 1975/76 Z80 available
• 1985 Z80 industrial standard
• 1992 Price less than 0.5 (1000)
• Now Z80 kernel for further developments
  as
• Single Chip Processors
• Why Z80? Chip area for CPU relatively small
• many peripherical processors
  available

normally not the functionality but the chip
area determines the price
3
"von Neumann" Architecture
4
Z80 CPU Pin Assignment
5
Minimal Configuration of a Microcomputer System
6
Z80-µP-Family (Typical Environment)

• PIO Parallel Input/Output DMA Direct Memory
  Access
• SIO Serial Input/Output CTC Counter/Timer
  Controller

7
Selected Boolean Functions (1)
8
Selected Boolean Functions (2)
9
de Morgan's Rule, Karnaugh-Veitch Diagram

• de Morgan's Rule

• Karnaugh-Veitch Diagram

10
Number Representations
The basic number set is binary B 0, 1
L, H Binary system
Octal System (grouping of 3 bits)
Hexadecimal System (grouping of 4 bits)
11
Binary Coded Decimal (BCD)

• BCD is using 4 Bit for 10 numbers

12
Transistor-Transistor-Logic (TTL)

• Inverter (7404)

• Avoidance of saturation
• effects by Schottky-TTL

13
TTL - Levels
14
Characteristics of Different Families
15
Emitter Coupled Logic (ECL)

• Differential Amplifier
• - input current independent of level
• - low signal delay (1ns typ.)

Level

• Disadvantages
• - high input current
• - low Störabstand

16
BiCMOS - CMOS
17
Typical Waveform
18
I / O Characteristics

• Electrically

IIH 20 µA (max.) at VIH 2,7 V
IOH 400 µA (max.) at VOH 2,7 V
IIL 400 µA (max.) at VIH 0,4 V
IOL 4 mA (max.) at VOL 0,4 V

• Propagation Delays

19
FCT - Logic

• FCT Fast CMOS, TTL compatible
• higher output power (68 48 mA)
• short delay (3ns)
• eg. FCT 244 (8 x Bus Driver)

• Problem caused by the high output current
• "Ground Bounce" effect
• switching an output is influencing the
  outputlevel of the other outputsreduced by an
  integrated resistor in the output

20
"Ground-Bounce" - Effect

• Avoidance
• small case layout (SMD)
• eg. QSOP L 3.5nH
• (Quarter Size Outline Package)
• current limiter
• 25R in the output
• adapted to line impedance

21
Open-Collector-Gates
Basic Output Circuit
Propagation delay of an Open Collector Output
"Wired OR"
22
Reset - Logic
23
Schmitt - Trigger
24
RS - FlipFlop
25
D - FlipFlop
26
JK - FlipFlop
27
BUS - System
28
Hazards
29
Memory - Global Organisation
30
Memory - Internal Organisation
31
EEPROM, Flash - RAM
32
Dynamic RAM Cell
33
Static RAM Cell
34
Dynamic RAM
35
UV Erasable PROM
36
DRAM Burst Access Mode
37
Interleaved Memory Banks (1)

• Basic Organisation

38
Interleaved Memory Banks (2)

• Typical Timing Diagram

39
Z80 CPU
40
Context Switch
41
Register Operations
42
ALU-Accelaration (1)

• Carry By Pass (CBP)

43
ALU-Accelaration (2)

• Carry Look Ahead (CLA)

44
Special Purpose Register
45
Control Section
46
Flag Register

• S Sign Flag (1negativ)
• Z Zero Flag (1Zero)
• H Half Carry Flag (1 Carry from Bit 3 to Bit
  4)
• P Parity Flag (1 Even)
• V Overflow Flag (1Overflow)
• N Operation Flag (1previous Operation
  wassubtraction)
• C Carry Flag (1 Carry from Bit n-1 to Bit
  n,with n length of operand)
• 2-complement number representation
• used in DAA-operation for BCD-arithmetic

47
DAA - Decimal Adjust Accumulator

• Adjusts the content of the Accumulator A for BCD
  addition and subtraction
• operations such as ADD, ADC, SUB, SBC, and NEG
  according to the table

All numbers hexadecimal
48
Number Representation

• r-Complement

(r-1)-Complement
In binary systems the value of r is 2.

• In 2-Compement-Systems an Overflow V can be
  determined by

49
Realisation of a Control Unit

• Asynchronous state machine
• - fastest solution
• - nearly impossible to design in complex
  applications(delays, hazards, races)

• Clock synchronous state machine
• Mealy automata

Moore automata - fast - complex design
process - in case of design errors or design
modificationsa complete new design process is
necessary Micro Programed Memory - most
flexible - easy to design and to modify - slow
50
Hardwired Control Unit (Mealy)
51
µP - CONTROL UNIT
52
Hardwired ? Microprogramed

• µ-programed

• Hardwired

53
Control Unit, Example (1)

• Task

54
Control Unit, Example (2)

• Corresponding State Diagram

55
Control Unit, Example (3)

• Corresponding Truth Table

56
Control Unit, Example (4)

• Logical Equations (State Variables - independent
  of TV)

57
Control Unit, Example (5)

• Logical Equations (Output Variables)

58
Control Unit, Example (6)

• Hardwired Solution (Mealy-state machine)

59
Control Unit, Example (7)

• Micro programed solution (type I)

60
Control Unit, Example (8)

• Micro programed solution (type I) - memory content

61
Control Unit, Example (9)

• Micro programed solution (type II)

62
Control Unit, Example (10)

• Micro programed solution (type II) - memory
  content

63
Advanced µ-Programed Techniques

• Encoding - Decoding

Some control points of the operational section
have inherent highly correlated dependencies.
Coding those lines and decoding them near the
control points will minimize the width of the
control vector.

• Vertical / Horizontal µ-Program Memory

Practically nearly 50 of the total µ-code memory
can be saved.
64
CISC - Complex Instruction Set Computer

• Charcteristics
• - many different instructions
• - different lengths of instructions
• - µ-programed control unit
• - high semantic level of instructions
• - orthogonal instruction set

65
RISC - Reduced Instruction Set Computer

• Charcteristics
• - constant cylcle machine instruction
• - short cycle time
• - same length for all instructions
• - hardwired control unit
• - Iinstructions mainly operate on register
  setload store operations for memory access

66
Instruction Processing

• Von Neumann cycle
• 1) instruction fetch
• 2) instruction decode
• 3) operand(s) fetch (if necessary)
• 4) instruction processing
• 5) computing address of next instruction

• Machine cycles of the Z80
• M1 fetch instruction code from memory
• M2 MR memory read
• M3 MW memory write
• I/O-R PR port read
• I/O-W PW port write

67
Opcode Fetch
68
Instruction Classes

• Data Transfer Group

• Arithmetic Group

• Logical and Rotate Group

• Branch Group

• Stack, I/O, and Machine Contol Group

• Exchange, Block Transfer, and Search Group

• Bit Manipulation Group

69
Data Transfer Group
Low Address (0700H) Least Significant Byte
(LSB) High Address (0701H) Most Signifikant
Byte (MSB)
70
Arithmetic Group
71
Logic and Rotate Group
72
Branch Group
PCh/l high/low order byte of PC
73
Stack, I/O, and Machine Control Group
74
Exchange, Block Transfer, and Search Group
75
Bit Manipulation Group
the Index at the register denotes the
bitpostion in that register
76
Structure of Instructions

• Every instruction consists of an operational Code
  (OP-Code)
• and -if necessary- an address part for the
  operand(s).

• Z80 OP-Code 1 Byte (exceptions in OPs using
  index registers
• the OP-Code is two bytes)
• the instruction set is not orthogonal

of addresses 0 R1 op R2 ? R31 (A) op
R ? R2 (A1) op (A2) ? R3 (A1) op
(A2) ? (A3) (A) contents of A, op binary
operation, ? transfer, A address, R register
77
Z80 Address Modes (1)

• Implied
• The instruction has only an OP-Code, the register
  is "implied"
• in the code
• eg CPL (Complement A) A ? A, OP-Code 2FH

• Register Direct
• The Instruction has only an OP-Code, both source
  and destination
• registers are defined in this code
• eg LD A,B (Load A with contents of B) A ? B,
  OP-Code 78H

Register Indirect The instruction has only the
OP-Code, the destination register is defined in
this code and a 16Bit register containing the
address of the source operand eg LD A,(HL) (Load
A from address contained in HL) A ? (HL), 7EH
78
Z80 Address Modes (2)

• Immediate
• The instruction contains the value of the operand
  immediately
• eg LD BC,1000H BC ? 1000H, Op-Code 01H 00H 10H
• eg LD A,1FH A ? 1FH, Op-Code 3EH 1FH

• Extended (Direct)
• The address of the operad is given
• as part of the instruction
• eg LD A,(1000H) A ? (1000H),
• OP-Code 3AH 00H 10H

79
Z80 Address Modes (3)

• Relative
• The address is relative to PC
• (only for Branches!)
• eg JR 10H PC ? PC 10H
• Op-Code 18H 0EH

Hint for JR e
80
Z80 Address Modes (4)

• Indexed
• The address of the operand is constructed from
  the index register
• (all instructions with index registers have 2
  byte OP-Codes!)
• eg LD A,(IX 10H) A ? (IX 10H,) Code DDH 7EH
  10H

81
Z80 Address Modes (5)

• Modified Page Zero
• A fixed address correspondence only used for the
  restart instruction
• eg RST 20H Stack ? PC, PCH ? 00H, PCL ? 20H,
• OP-Code E7H
• RST p Opcode 11 t 111 B with

• Bit
• Direct addressing of a bit for bit manipulations
• eg SET 3,A (Set bit 3 of A to 1) A3 ? 1, OP-Code
  CBH DFH
• (SET b,A Ab ? 1, OP-Code CBH 11 b 111B)

82
Z80 Address Modes (6)

• I/O Addressing
• Only with special I/O commands (IOREQ 1, MREQ
  0)
• eg IN A,(10H) A ? (n), OP-Code DBH 10H

Hint (A7, ..., A0) ? n and (A15, ..., A8) ?
A By loading A before using an I/O instruction
the available space for I/O-addresses can be
extended

• Sample Line from Instruction Set Listing

Symbolic Flags Opcode Mnemonic Operation
S Z H P/V N C 76 543 210 Hex ... ADD A,(HL) A ?
A(HL) ? ? X ? X V 0 ? 10 000 110 86 IN A,(n) A ?
(n) X X 11 011 011 DB ? n ?
... of Bytes of M Cycles of T
states Comments 1 2 7 2 3 11 n to A0 ?
A7 Acc. to A8 ? A15
83
Interactive Loops and Optimal Structures (1)

• General Structure

I Preparation, Initialization T Test, Conditio
nal Jump P Processing, Change of
Arguments J Unconditional Jump
Optimal Structures in Assembler - clearly
arranged programing - minimal amount of jumps
84
Interactive Loops and Optimal Structures (3)

• Repeat Loops

(the block P will be processed at least
once 'repeat until T')
3 2n 1
1 n
3 2n 1
3 2n 1
85
Programing Example (1)

• Task DE ? BC DE XY (16 bit, 2-Complement)
• XY transferred on STACK
• Call Call ADD_16
• result in DE, Status in F, all other registers
  not affected

• Basic Program Code

LD SP, FFFFh LD BC, FF56h LD DE, 7804h LD HL,
0105h PUSH HL CALL ADD_16 POP HL
The values of the Registers BC, DE, HL are
arbitrary numbers
86
Programing Example (2)

• Program

• Stack

ADD_16 PUSH IX save IX LD IX, SP IX frame
pointer PUSH AF save AF LD A, C A ? C ADD A,
E A ? C E LD E, A E ? C E LD A, B A ?
B ADDC A, D A ? B D Cy LD D, A DE ? BC
DE JP OV, ready P/V OV ? LD A, (IX 4) A ?
Y ADD A, E A ? E Y LD E, A E ? E Y LD A,
(IX 5) A ? X ADDC A, D A ? X D Cy LD D,
A DE ? DE XY ready PUSH AF AF ?
Stack LD A, (IX-4) A ? F Result LD (IX - 2),
A Stack (F) ? A POP AF clean Stack (1
word) POP AF restore AF POP IX restore IX RET
87
RAM, EPROM, I/O DECODING
88
I / O Methods

• Polling- simple implementation with I/O
  instructions- time consuming and wasting
  processing power
• Interrupt Processing- flexible reaction to
  asynchronous and slow I/O- implementation
  complex
• Direct Memory Access (DMA)- direct data transfer
  without CPU involved- very efficient with block
  transfer

89
Interactive Loops and Optimal Structures (2)

• Rejection Loops

(From the result of the test it might happen
that the loop never is entered 'while T do')
jump operations jumps in n iterations
2 2n 1
3 2n 2
2 n 2
90
Interrupts

• Maskable Interrupt (INT)

EI / DI Enable / Disable Interrupt(IFF ? 1 /
0) The interrupt signal INT only is accepted if
IFF1 1

• Nonmaskable Interrupt (MNI)

- always accepted, highest priority -
procedure IFF1 ? 0 (disable maskable
interrupt) branch to fixed absolute address
0066H (NMI-service routine) termination with
RETN (RETN is equivalent to RET additionally
IFF2 is copied to IFF1 to restore the state
of IFF before NMI IFF1 ? IFF2)
91
Maskable Interrupt

• Modes

IM0 8080-Mode, I/O-Device will deliver next
instruction(Call or RST n, n ? 00H,
08H,10H,18H,20H,28H,30H,38H) IM1 Service
Routine is expected at address 38H(equivalent to
RST 38H) IM2 I/O-Device will deliver an 8-bit
vector, that will pointtogether with the
I-register to a vector table

• Procedure

IFF ? 0 (disable interrupt) branch to
interrupt service routine (depending on mode)
service routine normally contains EI (at
least as last instruction before RETI,
interrupt not sampled at the end of EI and DI)
termination with RETI (RETI is logically
identical to RET because of different codes the
device can detect end of service routine by
monitoring the buses)
92
State of IFF1 and IFF2
not affected IFF IFF1 IFF2
93
Interrupt Mode 0

• Service Routine

n . . . . . .EIRETI
94
Interrupt Mode 1

• Service Routine

38H . . . . . .EIRETI
95
Interrupt Mode 2 (1)
P 8 bit interrupt vector - must be an even
binary number - programable
96
Interrupt Mode 2 (2)
97
INT - Processing
Interrupt (INT) finish processing of actual
instruction in M1 if IFF 0 then goto process
next instruction else continue IFF1 ? 0, IFF2 ?
0 Push PC on Stack acknowledge interrupt (IACK
M1 IOREQ 1) process service routine
(including EI) RETI
Mode 0 Mode 1 Mode 2 P ? (D7,D6,...,D0) PCL
? (I,P) PC ? 38H PCH ? (I,P1) IR ?
(D7,D6,...,D0) IR ? (PC) IR ? (PC)
98
Daisy Chaining (1)
1) no interrupt request i IEO
IEI 2) interrupt request i IEO 0 if IEI 1,
interrupt processed if IFF 1 if IEI 0,
interrupt not processed ("pending") 3) IACK M1
IOREQ indicates acceptance of
interrupt 4) detecting end of service routine by
M1 and EDH on data bus(EDH is first byte of
OpCode RETI or RETN) IEO IEI
99
Daisy Chaining (2)

• Nested Interrupts

100
Timer

• Typical Timer Applications

- time base (multi task system, sampling system,
...)- programable binary signal (eg serial
clock)- watchdog timer

• Watchdog

cyclic (in constant time periods) check, whether
program is alifetimer interrupt every x ms
Var WTDG Bzte WTDG_Service Watchdog
Serice-Routine begin if WTDG ltgt 0 then
Exeption_Handling else WTDG 1 eg
SW-Reset EI end INIT_WTDG Watchdog
initialisieren begin WTDG 0 INIT_TIMER
EI end
program loops(processing or waiting for events)
confirm watchdog (WTDG 0)
101
Direct Memory Access (DMA, 1)

• DMAC - Direct Memory Access Controller

To achieve datatransfer control without CPU, the
buses mustbe controlled by a DMA
Controller. The DMAC acts like an I/O device in
respect to the CPU DMAC contains severel (21 for
Z80DMAC) registers the CPUreads from and write
to those register via I/O commands DMAC can be
enabled for "Interrupt on Ready" Standard
I/O-Device controlling incl. INT and IEI /
IEO Additional Control Lines for Bus Mastering
(BUSRQ, BUSAK) including cascading (BAI,
BAO) During DMA CPU is idle(No Refresh
performed!, No interrupts are recognized!)
102
Direct Memory Access (DMA, 2)

• DMAC - Direct Memory Access Controller

The DMAC will be programed by CPU (mode, of
bytes,source address, destination addresss,
...) If source is ready (RDY) the DMAC will
request the buses (BUSRQ) similar to INT this
will be acknowleged by the CPU(BUSAK) and all
outputs of the CPU to busses are set to HZ. DMAC
is contolling the busses transparent to the
devices - memory to memory - memory to I/0 -
I/O to memory - I/O to I/O Modes - Burst (as
long as RDY 1) - Continuous (complete block,
RDY 0 DMA idle) - single (one byte) Bus is
released to CPU by BUSRQ 0
103
Example I/O Device Z80-PIO

• Programable Parallel Input / Output Device

104
Z80 PIO (2)

• Operating Modes

Mode 0 8 bit output port with 2 handshake
signalsMode 1 8 bit input port with 2
handshake signalsMode 2 bidirectional data
port with 4 handshake signalsMode
3 bit-programable I/O port without handshake
Port A bidirectional, Port B in mode 3

• Port Definitions

PORT B/-A CONTROL/-DATA Register
Selection 0 0 Port A Data 0 1 Port A
Control 1 0 Port B Data 1 1 Port B Control
105
Z80 PIO (3)

• Internal Control Bus Decoding

IORQ RD M1 Decoding 0 0 0 Inactive 0 0 1 Reset
0 1 0 Inactive 0 1 1 Instruction
Fetch 1 0 0 I/O Write 1 0 1 INT
Acknowledge 1 1 0 I/O Read 1 1 1 Inactive
106
Z80 PIO (4)

• Control Words

107
Z80 PIO (5)

• Task

Control of a simple process
V
A0
A1
p
A2
Process
A3
Z80 PIO
A4
A5
J
H
V Valve p Sensor for Pressure J Sensor for
Temperature H Heater
108
Z80 PIO (6)

• Task (continued)

A0 (Output) 1 Pressure exceeded 0 Pressure
ok A1 (Input) 1 Pressure ok 0 Pressure
exceeded A2 (Input) 1 Valve open 0 Valve
closed A3 (Input) 1 Temperature low 0
Temperature ok A4 (Input) 1 Temperature ok 0
Temperature low A5 (Output) 1 Heater on 0
Heater off A6,A7 not used B0-B7 not used
Interrupt Service Routine at addr
5080H Interrupt Vector Table starting at addr
1300H Relativ Entry Point of Vector for PIO is
16H Interrupt must be generated if
Temperature OR Pressure changed in such a way
that the state of the valve OR the heater must be
toggled Hardware Addresses of PIO-Ports Port
A Data "PIOAD" ACH Port A Ctrl "PIOAC"
ADH Port B Data "PIOBD" AEH Port B
Ctrl "PIOBC" AFH
109
Z80 PIO (7)

• Initialization

LD A,B7H B7H 1011 0111 B Out (PIOAC),A
load interrupt control LD A,09H 09H 0000
1001 B Out (PIOAC),A load interrupt
mask LD A,00H 00H 0000 0000
B Out (PIOAD),A reset Valve Heater EI
enable interrupt
DI disable interrupt IM 2 set interrupt mode
2 LD A,13H load I-register LD I,A LD H,13H
load pointer to LD L,16H vector
table LD (HL),80H load first address
of INC HL interrupt service rou- LD (HL),50H
tine to vector table LD A,16H 16H 0001 0110
B Out (PIOAC),A load interrupt
vector LD A,CFH CFH 1100 1111
B Out (PIOAC),A load PIO-mode LD A,1BH 1BH
0001 1011 B Out (PIOAC),A mode 3 load I/O mask
Initial Conditions - Interrupt
Control Interrupt with "Pressure exceeded" or
"Temperature Low" - Outputs "Valve closed" and
"Heater off"
110
Z80 PIO (8)

• Interrupt Service Routine

LD A,06H 06H 0011 0111 B Out (PIOAC),A
load interrupt control LD A,C get new
interrupt mask Out (PIOAC),A load interrupt
mask LD A,83H 83H 1000 0011
B OUT (PIOAC),A enable PIO interrupt POP BC
restore BC POP AF restore AF EI enable
interrupt RETI return from interrupt
ORG 5080H startaddress of service
routine DI disable interrupt PUSH AF save
AF PUSH BC save BC LD A,03H 03H 0000 0011
H OUT (PIOAC),A disable PIO interrupt IN A,(PIO
AD) get actual state CPL A complement of
A AND 1BH mask inverted inputs LD C, A new
interrupt mask inverted inputs AND 12H
mask for new outputs SLA A new
outputs Out (PIOAD),A write new outputs
(new states for Valve and Heater)