Ch.10%20SoC%20Design

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Ch.10 SoC Design
TAIST ICTES Program VLSI Design
Methodology Hiroaki Kunieda Tokyo Institute of
Technology
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System Design

• Behavior Description
• Behavior Partitioning
• Behavior Design (Algorithm design)
• Discrete Time?Quantization?Precision
• Power, Cost, Interface

High Level Synthesis

• Structure Design
• Parallel/Pipeline Processing
• High Level Synthesis (Scheduling/Allocation)
• SW/HW, Processor?ASIC?
• ASIP, IP

Optimal Realization for required System
Performance
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System Specification

• the clarification of any possible ambiguity
• the careful definition of the project scope
• approximated costs for development
• Identification of competition
• subsequent improvement on their capabilities

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System Design

• Target Platform / Computation model
• ASIP, Processor with or without RTOS, ASIC, FPGA
• Fixed Point Arithmetic
• Multiplication/ Division
• Memory
• Pin Assignment

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10.1 Algorithm DesignSystem Development
ToolSystem Description LanguageHardware
Oriented Algorithm
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a. System Development Tool MATLAB/SIMULINK

• MATLAB is a high-level technical computing
  language and interactive environment for
  algorithm development, data visualization, data
  analysis, and numeric computation.
• Using the MATLAB product, you can solve technical
  computing problems faster than with traditional
  programming languages, such as C, C, and
  Fortran.

Control, DSP, Image Processing, Communication,
Neural Network, Statics, Optimization,
Differential Equations
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Key Features

• High-level language for technical computing
• Development environment for managing code, files,
  and data
• Interactive tools for iterative exploration,
  design, and problem solving
• Mathematical functions for linear algebra,
  statistics, Fourier analysis, filtering,
  optimization, and numerical integration
• 2-D and 3-D graphics functions for visualizing
  data
• Tools for building custom graphical user
  interfaces
• Functions for integrating MATLAB based algorithms
  with external applications and languages, such as
  C, C, Fortran, Java, COM, and Microsoft Excel

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b. System Description Language
include "systemc.h SC_MODULE (up_down_counter)
//-----------input ports---------------
sc_in ltboolgt clk sc_in ltboolgt reset sc_in
ltboolgt enable sc_in ltboolgt up_down
//------------output ports---------------
sc_out ltsc_uintlt8gt gt out //------------internal
variables-------- sc_uintlt8gt count
//--------------process declaration-------
void counter () if (reset.read())
count 0 else if
(enable.read()) if
(up_down.read()) count count
1 else count count - 1
out.write(count)
//-------------process registration--------
SC_CTOR(up_down_counter) SC_METHOD
(counter) sensitive ltlt clk.pos()
Up-down Counter by SystemC
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SystemC

sc_prim_channel is the base class for all primitive channels, and provides such channels with unique access to the update phase of the scheduler. This standard provides a number of predefined primitive channels to model common communication mechanisms. Some of them are sc_mutex sc_fifo sc_semaphore
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c. Hardware Oriented Algorithm Inner Product
Distributed Arithmetic-

• Hardware Algorithm for Inner Product
• DFT, DCT, Digital Filters
• Basic Idea
• Input data is decomposed into a group of bits. By
  replacing order of
• calculation in such a way that multiplication
  between coefficent and each
• bit is performed and accumulated at first
  and accumulate the results with shifting.

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Bit Manupilation

• Inner Product
• Bit 2s complement Representation of xn
• By substituting and changing an order of
  operations as,

Realized by ROM with N-bits address and NBc-bits
data
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Inner Product Circuit
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8 point DCT Implementation
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10.2 Architecture Design a. High Level
Synthesis b. ASIP Design c. FPGA Design
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a. High Level Synthesis
Software Language (C/C, System C)
simulation is available on PC.
CDFG Control and Data flow Graph is
constructed.
Scheduling to decide the time and Op unit
for each operation.
Allocation to decide registers or memory
to store the data
Output Data path and its control logic
circuit are derived.
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Example Directed acyclic graph
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Example Scheduling
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Example Binding(allocation)
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Example Final Data-Path
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Example Controller
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Hardware Cost

• Area or hardware
• Delay or Speed
• Power

Critical path
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Schedule Methods
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b. ASIP Design with LISA
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c. FPGA Design
RTL
RTL Simulation
Logic Synthesis
Synthesis Netlist
LSI Tool
Functional Verification
FPGA Tool
Gate Assignment LE Place and Rout
Configuration Data
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END
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Systolic Algorithm
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Alternative Method

• Systolic Array
• Low parallel Efficiency
• inefficient Data Memory
• Bottle Neck for I/O
• PE number uniquely decided
• Restricted to local communication between PEs
• Memory Sharing Processor Array (MSPA)
• High parallel Efficiency
• Minimization of Data Memory
• Restriction to I/O ports
• Restriction to PE number
• Not restricted to local communication

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MSPA Theory
Find out appropriate cordinate Of Time and Space,
which may Not violate the precedence Relation
between operations.
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Comparisons
Matrix Product Case
Size Systolic Systolic Systolic MSPA MSPA MSPA
Size time PE Parallel Efficiency time PE Parallel Efficiency
4 19 10 34 34 2 94
10 109 28 33 208 5 96
50 1,717 49 33 8,425 18 98
201 15,001 1401 39 80,801 101 100
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Widow-MSPA I
Image

• MSPA for Widow Operation
• Minimize I/O ports and decide PE
• Fast Parallel Operation
• Flexible PE and processing time
• Applicable various Image Processing such as
  motion vector search

Window
??
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Widow-MSPA II
WINDOW--MSPA
Input Network
External Image Data Memory
Output Network
External Output Data Memory
WINDOW-MSPA ARCHITECTURE
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Widow-MSPA??3(1996-1998)
? ? ? ? ?
? ? ? ? ?
?
?
?
?
?
?
?PE00?????9???????????(1?????1?---) ?PE01?????9???
????????(???1???????) ?PE02?????9???????????(???1?
??????) ?PE03?????9???????????(???1???????) ?PE04?
????9???????????(???1???????) ?PE11?????9???????
????(???3???????)
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Operation of Window-MSPA

Clock 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Global/IO_0 (0,0) (0,1) (0,2) (0,3) (0,4) (0,5) (0,6) (3,0) (3,1) (3,2) (3,3) (3,4) (3,5) (3,6) (6,0) (6,1) (6,2) (6,3) (6,4) (6,5) (6,6)
Global/IO_1 (1,0) (1,1) (1,2) (1,3) (1,4) (1,5) (1,6) (4,0) (4,1) (4,2) (4,3) (4,4) (4,5) (4,6)
Global/IO_2 (2,0) (2,1) (2,2) (2,3) (2,4) (2,5) (2,6) (5,0) (5,1) (5,2) (5,3) (5,4) (5,5) (5,6)

Local/IO.00 (0,0) (0,1) (0,2) (0,3) (0,4) (0,5) (0,6) (3,0) (3,1) (3,2) (3,3) (3,4) (3,5) (3,6)
Local/IO.01 (1,0) (1,1) (1,2) (1,3) (1,4) (1,5) (1,6) (4,0) (4,1) (4,2) (4,3) (4,4) (4,5) (4,6)
Local/IO.02 (2,0) (2,1) (2,2) (2,3) (2,4) (2,5) (2,6) (5,0) (5,1) (5,2) (5,3) (5,4) (5,5) (5,6)


PE(0,0) PE(0,0) PE(0,0) PE(0,0) PE(0,1) PE(0,1) PE(0,1) PE(0,1) PE(0,2) PE(0,2) PE(0,2) PE(0,2)



Local/IO.10 (1,0) (1,1) (1,2) (1,3) (1,4) (1,5) (1,6) (4,0) (4,1) (4,2) (4,3) (4,4) (4,5) (4,6)
Local/IO.11 (2,0) (2,1) (2,2) (2,3) (2,4) (2,5) (2,6) (5,0) (5,1) (5,2) (5,3) (5,4) (5,5) (5,6)
Local/IO.12 (3,0) (3,1) (3,2) (3,3) (3,4) (3,5) (3,6) (6,0) (6,1) (6,2) (6,3) (6,4) (6,5) (6,6)


PE(1,0) PE(1,0) PE(1,0) PE(1,0) PE(1,1) PE(1,1) PE(1,1) PE(1,1) PE(1,2) PE(1,2) PE(1,2) PE(1,2)

Local/IO.20 (2,0) (2,1) (2,2) (2,3) (2,4) (2,5) (2,6)
Local/IO.21 (3,0) (3,1) (3,2) (3,3) (3,4) (3,5) (3,6)
Local/IO.22 (4,0) (4,1) (4,2) (4,3) (4,4) (4,5) (4,6)


PE(2,0) PE(2,0) PE(2,0) PE(2,0) PE(2.1) PE(2.1) PE(2.1) PE(2.1) PE(2,2) PE(2,2) PE(2,2) PE(2,2)

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Widow-MSPA??1(1996-1998)
??????????22x22
Widow ??? ????????? ????????? ????????? Window-MSPA Window-MSPA Window-MSPA
Widow ??? ???? ???? (??????) ???? ???? ???? (??????) ????
3x3 809 9 (2) 49 66 63 (9) 87
8x8 514 64 (7) 44 176 120 (3) 68
16x16 354 256 (15) 14 352 49 (2) 73
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Example 1. Line Direction
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Problem Description
Problem Find out a 3x3 direction type, Which
is included the most among Line pattern in target
image.
Software Solution To count the number of
direction Types among the line pattern In the
target image.
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Hardware Solution
1. Describe a direction pattern by 9 bit signals
such as (000111111) for the first direction
type. 2. Use each direction pattern as 9 bit
address data of ROM, whose data is a
increment signal of corresponding accumulation
registers.
Direction of Line pattern
Increment signals
ROM Address 9 bits Data 24 bits
Direction Type 0
Select the largest number in the registers
Direction Type 1
Direction Type 2
Direction Type 23