PRR%20QA/QC

1
Detector DAQ Status
Jean-Sebastien Graulich, Geneva

• Since CM17
• Detector DAQ software
• Front End Electronics
• Schedule Milestones
• Summary

2
Since CM17

• DAQ architecture revision
• DAQ Software Development DATE is running
• Readout code for TDC V1290 and Trigger Receiver
  (V977)
• Test bench is taking TDC V1290 data in
  multi-event mode with faked spill structure
• Shaper production prototype
• Assembled in Sofia
• Tested in Geneva
• Splitter prototype tested

3
DAQ Architecture revision

• Local Storage (3 TB)
• inside the Event Builder

All the hardware for stage I in hand
4
DATE Vocabulary

• LDC Local Data Concentrator
• The PC connected to the VME crate via the PC-VME
  Interface
• GDC Global Data Collector
• Event Builder
• Trigger Receiver
• IO Register (with several inputs), present in
  each VME crate, receiving the signal informing
  the LDCs that something has happened, e.g the
  spill is finished and the data should be readout
  ( Physics Trigger). It also handles busy
  signals.
• Event Type
• Tag attached to the event depending on which
  trigger receivers input has received a signal
• Event
• DATE Event DAQ Event !!! A Physics Event
  contains data for several Particle Events (about
  600)

5
Particle Trigger Revision

• The timing of the trigger should be given by the
  burst
• Delay TOF0, TOF1 TOF2 such that they arrive
  approximately at the same time in the trigger
  logic
• Make the TOF logic pulses 200 ns long
• Make the Burst Gate narrow and Delay it such that
  it arrives more than 100 ns after the TOF signals
• All single raw time distribution will be 100 ns
  wide

Burst Gate
200 ns
TOF0
TOF1
TOF0 ? TOF1 ? Burst Gate
6
LEFT Pmts
OR of 10 slabs
UP and DOWN Pmts are not used for the trigger
2 by 2 coincidence
RIGHT Pmts
7
Selection of Particle Trigger Condition
TOF0
OReg0
TOF1
OReg1
Particle Trigger Request
TOF2
OReg2
DT-Gate
Particle Trigger
Burst Gate
Downscale 1/128
OReg3
FEE Busy
SW Controlled Clock
OReg4

• Example
• Oreg1-4 0 Clock trigger
• Oreg1-4 1 Burst Gate ? TOF0 ? TOF1 ? TOF2 ?
  DS Burst Gate

8
DAQ Trigger Design

• DAQ is designed to allow sub-detectors to take
  local Calibration Events in between spills
• Double care is taken to keep synchronization
  between LDCs
• Possible cause for de-synchronization
• DAQ trigger arrives while one LDC is still busy
  with the readout of the previous (quite easy to
  avoid)
• One DAQ trigger is lost in transmission
  (unpredictable)
• Design such that any misalignment is detected
  right away

9
MICE Systems synchronization (Updated)
MICE Ready
DAQ Ready
Target Ready
RF Ready
Spill Request
20 ms
Extraction
Gated Machine Start
Validated Machine Start
Target Delay
Target Trigger
Protons on target
RF Delay
RF Trigger
RF Power
DT Delay
DT Gate
DAQ Trigger
10
Flexibility requirement

• There should be a safe way to bypass the
  synchronization procedure. E.g.
• DAQ running without beam
• Target tests when DAQ is off
• Etc
• The bypass mechanism should be under central
  control

11
Bypass Logic Scheme
DAQ Ready
OReg5
RF Ready
OReg6
Target Trigger
Target System
Start of Spill Trigger
VMS
Target Ready
OReg7
RF Trigger
MCM Ready
OReg8
Delay
GMS
1Hz Clock
OReg9

• A small stand alone application will allow
  setting OReg5-9 of the trigger selection module
  in the central Trigger VME crate
• At Start of Run, the DAQ will check these
  registers and send warnings if one is set

12
DAQ trigger distribution
VMS
Fixed delay
SOS Trigger
Fan out to LDCs

Target Trg
Software Check No overlap with SOS busy
(otherwise stop with error)
Fixed delay few ms
Particle Triggers
Fixed width 1 ms
Physics Event DAQ Trigger
Fan out to LDCs
Depends on Data Size
1 s
EOS Trigger
Fan out to LDCs
DAQ Idle DAQ Ready
13
CAEN V977 Channels 0-7 configured as Flip-Flop,
reset by software
14
Front End Electronics

• Shaper Production prototype
• 1 PCB board designed, drawn and produced in Sofia
• Fully equipped manually in Sofia
• 4 channels with 4 stages of filtering
• 12 channels with 2 stages of filtering
• Different gains
• A jumper allow choosing Single-ended (for TOF) or
  differential (for EMCal) inputs
• All channels fully operational
• Tested for
• Internal Noise OK ( 400 mV RMS)
• Gain stability OK
• Impedance Matching (120 Ohms) OK
• Offset Stability OK (lt 500 mV over several days)
• Cross talk 22 Db between adjacent
  channelsmainly do to induction at the input ?
  minor design change to reduce it further

15
Main contribution from Ilko Rusinov and Andrey
Marinov (shaper)Pierre Bene (splitter)
16
Shaper Test Outcomes

• Shaper design is validated
• The 4-stages version is more appropriate
• Larger signal rise time for identical full width
  ? better for time measurement for EMCal
• Not significantly more noisy
• EMCal and TOF have different dynamic range and
  need different gains
• A jumper will be added to select low gain for
  EMCal or larger gain for TOF
• Splitter needs a second iteration
• Gain matching is fine
• Pick up noise is too large -(mainly 50 Hz)

17
Shaper optimization

• There was a long discussion about dynamic range
  and gain issues
• Output range of the shaper is limited by the
  power supply voltage provided by the NIM crate
• /- 6V -gt Maximum 2 Volts output range
• /- 12V -gt Maximum 8 Volts output range
• We cant use /- 12V for all the channels because
  the current is limited to 3A and we need 700 mA
  per board
• EMCal input signal range is 5V
• TOF input signal range is 2V
• Input range of the CAEN flash ADC is either
  2.25V or 10 V. Which version should we ask for ?
• We will start with the small input range version
  of the fADC
• shapers gain of 0.5 for EMCal and 1.0 for TOF
• Power supply voltage will also be selectable by a
  switch

18
Schedule Milestones

• DAQ Test bench including Event builder Feb 2007
• Still not completely passed
• Significant progress done with the single PC test
  bench
• Order Hardware for Stage 1 March 2007
• done in May but everything is already delivered
• Shaper production process launched
• Launch Shaper Production June 2007
• Move DDAQ system to RAL July 15 2007
• First batch of 6 Shaper Boards (96 ch) September
  2007
• Production of 8 Splitter boards September 15
  2007

19
Summary

• DDAQ Architecture has been revised
• All the hardware for Stage I is in hand
• DAQ test bench is so late that its becoming
  obsolete
• Particle and DAQ Trigger designs are now mature
• Shaper is in good shape
• DAQ system will be installed at RAL in July

20
Questions suggestion after the talk

• Trigger condition Add downscaled TOF 0 in OR
• Send actual condition used to issue the trigger
  into IR
• Use TOF vertical counters in OR with the
  Horizontal
• A list of requirements should be issued