CPLD????

1
CPLD????
? ? ? ????????
2
? ? ? ?

• ?????????
• ??????????
• ????(MOORE)?????VHDL???
• ????(MEALY)?????VHDL???

3
8.1 ??????
?????(?????)????????,???????????????,????
??????????,???????????????????,???????????????????

4
8.2 ????????

• ????????????????????????????
• ?????????????
• ?????????????????????
• ????VHDL???????
• ??????????,????????????
• ??????,??????????????

5
8.3 ?????

• ?????????????,?????????
• ??(Moore)????--??????????
• ??(Mealy)????--??????????????

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8.4 Moore????????
More?????????????????,???????,?
?????????????
?????????
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8.4 Moore????????
???????????????????????1101?,??????1,????0?
??????? ? ??????,???????? ? ??????? ?
?VHDL????????
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(1) ??????,???????? ????????(0) S0
???????(1) S1 ?????????(11) S2
?????????(110) S3 ?????????(1101) S4
8.4 Moore????????
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(2) ?????
8.4 Moore????????
1101
0
S0/0
1
0
0
S1/0
S4/1
1
0
1
1
1
S2/0
S3/0
0
10
8.4 Moore????????
(3)?VHDL???????

• ????????????TYPE??????????,?
• TYPE states IS (st0, st1, st2, st3,
  st4, st5)
• SIGNAL present_state, next_state
  states
• ?????????????????????????????????????????????????
  ???,??,???????????????????????,?Reset???
• ???????????????????????????(????????????????????)
  ???????current_state???????next_state?????,???????
  ????????????????
• ????????????????????????????????????????,????????
  ????

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LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTIT
Y moore IS PORT( clk, dataIN STD_LOGIC
zo OUT STD_LOGIC) END moore ARCHITECTURE a
OF moore IS TYPE STATE IS (S0,S1,S2,S3,S4) SIGN
AL current_state,next_state STATE BEGIN p1
PROCESS(clk) BEGIN IF (clk'EVENT AND
clk'1') THEN current_stateltnext_stat
e END IF END PROCESS p1
?????
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p2PROCESS(current_state,data) BEGIN CASE
current_state is WHEN S0gt IF data'1' THEN
next_stateltS1 ELSE next_stateltS0
END IF WHEN S1gt IF data'1' THEN
next_stateltS2 ELSE next_stateltS0
END IF WHEN S2gt IF data'0' THEN
next_stateltS3 ELSE next_stateltS2
END IF WHEN S3gt IF data'1' THEN
next_stateltS4 ELSE next_stateltS0
END IF WHEN S4gt IF data'1' THEN
next_stateltS1 ELSE next_stateltS0
END IF END CASE IF
currents4 then Z0lt1 END PROCESS p2 END
a
??????
??????
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8.4 Moore????????
? ? ? ?
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8.4 Moore????????
????????????,?A???B????????????,?10?????????????
A?? B??
? ?
? ?
? ?
? ?
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8.4 Moore????????
???????????
?? A?? (???) B?? (???)




?? A?? (???) B?? (???)
S0 0 1 0 1 0 0
S1 0 0 1 1 0 0
S2 1 0 0 0 1 0
S3 1 0 0 0 0 1
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???????
8.4 Moore????????
S0 010100
S1 001100
S3 100001
S2 100010
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8.4 Moore????????
????
LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTIT
Y jtd IS PORT( clkIN STD_LOGIC ZOOUT
STD_LOGIC_VECTOR(5 DOWNTO 0)) END jtd
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?????
ARCHITECTURE a OF jtd IS TYPE STATE IS
(S0,S1,S2,S3) SIGNAL pstate STATE
BEGIN PROCESS(clk) BEGIN IF (clkEVENT
AND clk1) THEN CASE pstate is
WHEN S0gt pstateltS1 WHEN S1gt
pstateltS2 WHEN S2gt pstateltS3
WHEN S3gt pstateltS0 END CASE
END IF END PROCESS
??????
??????
ZOlt010100 WHEN pstates0 ELSE
001100 WHEN pstates1 ELSE 100010
WHEN pstates2 ELSE 100001 END a
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8.5 Mealy????????
Mealy?????????????????,??????????,?
?????????????????
???????
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? ?????
8.5 Mealy????????
1101
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8.5 Mealy????????
????
LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTIT
Y mealy IS PORT( clk, dataIN STD_LOGIC
zo OUT STD_LOGIC) END mealy
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ARCHITECTURE a OF mealy IS TYPE STATE IS
(S0,S1,S2,S3,S4) SIGNAL pstate STATE BEGIN
PROCESS(clk) BEGIN IF (clkEVENT AND
clk1) THEN CASE pstate is WHEN
S0gt IF data1 THEN pstateltS1 ELSE
pstateltS0 END IF zolt0 WHEN
S1gt IF data1 THEN pstateltS2 ELSE
pstateltS0 END IF zolt0 WHEN
S2gt IF data1 THEN pstateltS2 ELSE
pstateltS3 END IF zolt0
WHEN S3gt IF data1 THEN pstateltS4 zolt1
ELSE pstateltS0 zolt0END IF WHEN S4gt IF
data1 THEN pstateltS1 ELSE pstateltS0
END IF zolt0 END CASE END
IF END PROCESS END a
Mealy? ?????
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? ?

• ???????????????????
• ??????????????
• ???????????????????
• ???????????????????????
• ?????????????????????VHDL??
• VHDL????????????????