PLDT2 TRAINER

1
PLDT-2 TRAINER

• What you need to know to use it.

2
EPM7128SLC84

• CPLD
• PLCC 84 pin package
• Can be erased.
• Can be reprogrammed on the board
• 128 macrocells
• 2500 usable gates
• 2 to 15ns propagation delay
• Ouputs up to 25mA
• Needs CAD software to program it

3
PLDT-2

• Uses EPM7128SLC84 CPLD
• Connects to microcomputers parallel port
• Needs 25-wire cable with male DB-24 connectors on
  both ends.
• Board functions alone after download
• All CPLD signal pins available (at HD4, HD5, HD6,
  and HD7 receptacles)
• DIP switches,push-buttons, 7-segment displays,
  and LEDs for testing
• Clock runs at 4MHz
• Requires 7-9VDC 1A power supply

4
MAP
Power Receptacle
DB-25
4MHz clock
EPM7128SLC-15
5
INPUTS

• DIP switch SK1 provides digital level inputs (1
  or 0)
• When DIP is OFF, HD1 is connected to Vcc (5VDC)
  through a pull-up resistor RN1.
• When DIP is ON, HD1 and J2 are connected to
  ground.
• Jumpers on HD1 connect DIP SK1 to the CPLD.

6
MAP
HD1 RN1 DIP SK1 J2
7
INPUTS

• Each switch segment on SK1 connects through HD1
  to the CPLD.

Note These are not the only pins on the CPLD
that can be used for inputs. They are just the
ones connected to HD1.
8
INPUTS

• Four debounced toggle switches on module S5. When
  Off a switch provides a TTL high to J12 and
  lights an LED.
• Normally open push-button switches S3 and S4 are
  NOT DEBOUNCED. They produced a TTL low until
  pressed, then they produce a TTL high.

9
On-board clock

• 4MHz
• Normally Connected to pin 83 of CPLD through
  jumper JP1.
• Available at socket labeled CLK

Pin 83
10
Outputs

• 8 red LEDs connect to HD2 through current
  limiting resistors RN3.
• CPLD signals output signals are available at J4
• HD2 is normally connected to the CPLD

11
Outputs
Note These are not the only CPLD pins that can
be used as outputs. They are just the ones
connected to HD2.
12
7-SEGMENT DISPLAY

• Common-anode
• Connected to CPLD through current-limiting
  resistors