Silicon Overview

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Xilinx Silicon
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Xilinx Family features

• High performance at 3.3V and 5V
• Footprint compatibility
• Devices within each family are compatible
• Tolerant of pin locking
• Low power consumption/high performance
• Integrated software
• Technology independence
• EDIF, VHDL, Verilog, SDF interfaces

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Xilinx IC Product Solutions

• XC4000X series - Industrys largest and fastest
  FPGAs
• XC4000EX - 0.5 ?m, 5 V devices
• XC4000XL - 0.35 ?m, 3.3 V devices, 5 V compatible
  I/O
• XC4000XV - 0.25 ?m, 2.5 V / 3.3 V devices, 5 V
  compatible I/O
• Low-cost solutions
• SPARTAN - UltraDenseTM 0.5?m , 5 V device
• SPARTANXL - UltraDenseTM 0.35?m , 3.3 V device, 5
  V compatible I/O
• HardWire
• XC9500 - Flash-based ISP CPLD family
• Lowest price, best pin locking CPLD product

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XC4000 Family Features

• Synchronous Single and Dual-Port RAM
• Internal Tri-state Buffers
• IEEE 1149.1 JTAG Boundary Scan
• System performance to 80 MHz (-09)
• 1/ (T setup Tclk-out)

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XC4000X SeriesHigh Density Leadership
XC4000EX Family XC4000XL Family XC4000XV
Family Logic Cells 2,432 - 3,078 466 -
7,448 10,982 - 20,102 Max Logic Gates 28,000 -
36,000 5,000 - 85,000 120,000 - 220,000 Typ Gate
Range 50,000 - 65,000 9,000 - 180,000 220,000 -
500,000 (Logic Select-RAM) I/O 256 - 288 112 -
448 288 - 448 Number of Devices 2 10 4 Power
Supply 5 V 3.3 V 3.3 V 2.5 V I/O Interface 5
V 5 V / 3.3 V 5 V / 3.3 V
1 Logic Cell 1 4-input SRAM 1 Flip-Flop
1 Logic Gate 12 2 input NAND gates
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XC4000 Families

• XC4000XV, XC4000XL and SPARTAN are recommended
  for all new designs

1 Logic Gate 1 4-input SRAM 1 Flip-Flop
1 Logic Gate 12 2 input NAND gates
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XC4000 Series FPGA Architecture
100 Footprint Compatible
20-25 of CLBs as RAM
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Configurable Logic Block (CLB)

• Combinatorial logic is implemented in Look-up
  Tables
• Also known as Function Generators
• Look-up Tables can be used as synchronous RAM
• Output registered and/or combinatorial

G_LUT
H_LUT
F_LUT
FFY
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Look-Up Tables

• Combinatorial Logic is stored in Look-up Tables
  (LUTs) in a CLB

• Capacity is limited by number of inputs, not
  complexity
• Delay through CLB is constant

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Single-Port RAM

• Synchronous write, Asynchronous read
• 16x2 or 32x1 max per CLB

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Dual-Port RAM

• One common synchronous write port
• Two asynchronous read ports
• 16x1 max per CLB

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I/O Block (IOB)

• Identical I/O Blocks on periphery of die
• Input, output, or bi-directional
• Registered, latched, or combinatorial
• Three-state output
• Programmable output slew rate

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IOB Features

• Registered, latched, or direct input
• Registered or direct output
• Clock enable on both registers
• Programmable fast slew rate
• Default slow for noise reduction
• Programmable TTL or CMOS thresholds
• Input and output default TTL
• Tri-state output buffer
• Controlled locally or by global GTS

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Programmable Interconnect

• Resources to create arbitrary interconnection
  networks
• Various types of interconnect
• Flexible general-purpose interconnect
• Low-skew long lines
• Internal three-state buffers for buses and wide
  functions

CLB
CLB
Switch Matrix
CLB
CLB
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Special Resources

• Global clock buffers
• High speed, low skew buffer networks
• Can also be used for high fanout logic signals
• Global reset net
• Global Reset connects to all Flip-Flops and
  Latches
• Global Tri-state connects to all IOB tri-states
• Special resources
• Tri-state drivers
• Wide decode or cascade functions
• Boundary scan

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XC4000XL Family
4005XL 4010XL 4013XL 4020XL 4028XL Logic
Cells 466 950 1,368 1,862 2,432 Typ.Gate Range
3 - 9K 7-20K 10-30K 13-40K 18-50K (Logic
Select-RAM) Max. RAM bits 6K 13K 18K 25K 33K (no
Logic) I/O 112 160 192 224 256 4036XL 4044XL 405
2XL 4062XL 4085XL 40125XV Logic Cells 3,078
3,800 4,598 5,472 7,448 10,982 Typ Gate Range
22-65K 27-80K 33-100K 40-130K 55-180K 78-250K (L
ogic Select-RAM) Max. RAM bits 42K
51K 62K 74K 100K 158K (no Logic) I/O 288
320 352 384 448 544
20-25 of CLBs as RAM
25-30 of CLBs as RAM
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XC4000XL Footprint and Packaging Leadership
4005XL 4010XL 4013XL 4020XL 4028XL 4036XL
4044XL 4052XL 4062XL 4085XL PC84 PC84 PQ100 PQ1
00 VQ100 TQ144 TQ144 HT144 HT144 PQ160 PQ160 PQ160
PQ160 HQ160 HQ160 HQ160 TQ176 HT176 HT176
PQ208 PQ208 PQ208 PQ208 HQ208 HQ208 HQ208 PQ240
PQ240 HQ240 HQ240 HQ240 HQ240 HQ240 HQ304 HQ3
02 HQ304 HQ304 HQ304 BG256 BG256 BG256 BG256
BG352 BG352 BG352 BG432 BG432 BG432 BG432
BG560 BG560 BG560
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XC4000EX/XL Interconnect Hierarchy Fast,
Segmented Resources For Uniform Implementation
Routing Resource XC4000X Spartan V/H Quad
Line 12/12 0/0 V/H Long Line
10/6 6/6 V/H Direct Connects
2/2 0/0 V/H Single Line 8/6 8/6 V/H
Double Line 4/4 4/4 Vertical Global
Lines 8 4

• Abundant high-speed, segmented interconnect
• Optimized resources for high-density designs
• Delivers fast compilation times and ensures high
  first-pass completion rates

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XC4000EX/XL Clocking Options
Global Low-Skew Buffers
Global Early Buffers
Ideal for system clocks or critical control
signals
High speed clock for localized macros or cells
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Spartan Family

• Low cost in high volumes
• Features
• Single and dual port Synchronous RAM
• 100 MHz internal speeds
• 100 MHz Pipelined Multipliers
• 66 MHz PCI
• Support of Intellectual Property (ready-to-use
  functions)
• 3.3 Volt and 5 Volt operation

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Basic Architecture

• Array of CLBs surrounded by perimeter IOBs
• Special functions in corners

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Spartan Introduction
Spartan (5V)
Spartan-XL (3.3V)
Available XCS05 NOW XCS10 NOW XCS20 NOW XCS3
0 NOW XCS40 NOW Software support - Now
Available XCS05XL 3Q98 XCS10XL 3Q98 XCS20XL
3Q98 XCS30XL 3Q98 XCS40XL 3Q98 Software
support in A1.5 (2Q98)
Cores and Implementation Software available
before silicon
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Xilinx Spartan Series
5 Volt -gt XCS05 XCS10 XCS20
XCS30 XCS40 3.3 Volt -gt
XCS05XL XCS10XL XCS20XL XCS30XL
XCS40XL System Gates 2K-5K 3K-10K 7K-20K 10K-30
K 13K-40K Logic Cells 238 466 950 1368 1862 Max
Logic Gates 3,000 5,000 10,000 13,000 20,000 Flip-
Flops 360 616 1120 1536 2016 Max RAM
bits 3,200 6,272 12,800 18,432 25,088 Max
I/O 80 112 160 192 224 Performance 80Mhz 80Mhz 80M
hz 80Mhz 80Mhz
No Compromises Performance, RAM, Cores, and Low
Price
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Spartan Series Footprint Compatibility

• Highest volume ASIC plastic packages
• Footprint compatible in common packages

5 Volt XCS05 XCS10 XCS20 XCS30 XCS40 3.3
Volt XCS05XL XCS10XL XCS20XL XCS30XL XCS40XL PC8
4 PC84 VQ100 VQ100 VQ100 VQ100 TQ144 TQ144 TQ1
44 PQ208 PQ208 PQ208 PQ240 PQ240 BG256
BG256
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Spartan Speed Grades

• Higher Spartan speed grade higher performance
• Higher performance Spartan-5 speed grade
  available in 98

S-4
E-1

• Spartan-4 faster than XC4000E-1
• Spartan-3 faster than XC4000E-2
• Spartan much faster than 5200

S-3
E-2
Performance
-3
-4
5200 4000E Spartan
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XC9500 FastFlash Family

• First 5V Flash in-system programmable CPLD
• Extended IEEE 1149.1 JTAG for programming, test,
  and manufacturing
• High performance 5 ns pin-to-pin
• High density - Up to 6,400 usable gates
• Industrys best pin-locking architecture
• Highest reprogramming reliability
• 10,000 program/erase cycles
• 20-year data retention

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XC9500 Product Offering
0.6µ/0.35µ CMOS FLASH
95144
95216
95288
9536
9572
95108
Macrocells
36
72
108
144
216
288
Usable Gates
800
1600
2400
3200
4800
6400
tPD (ns)
5
7.5
7.5
7.5
10
15
Registers
36
72
108
144
216
288
Max. User I/Os
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72
108
133
166
192
100TQ 100PQ 160PQ
Packages
44VQ 44PC
44PC 84PC 100TQ 100PQ
84PC 100TQ 100PQ 160PQ
208HQ 352BG
160PQ 208HQ 352BG
Available
Now
Now
Now
Now
Now
1Q98
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CPLD Family PerformanceRoadmap
Fastest Speed
Family
Process
Voltage
tPD
fSYS
I/Os
XC9500
5V
5ns
100 MHz
Mixed system capability
0.6µ
XC9500
5V
5ns
100 MHz
Mixed system capability
0.5µ/0.35µ
XC9500XL
3.3V
4ns
175 MHz
5 volt compatible I/Os
0.35µ
XC9XX X(K2)
2.5V
225 MHz
3.3 volt I/O, 5 volt compatible
0.25µ
lt4ns
Can safely drive 3 volt devices when in TTL
mode Can be safely driven with 5 volt logic
and can drive TTL levels
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XC9500 Uniform Architecture
3
JTAG Controller
In-System Programming Controller

• Identical I/Os
• Identical FBs
• Identical macrocells

JTAG Port
Function Block 1
I/O
I/O
Function Block 2
I/O
I/O Blocks
FastCONNECT Switch Matrix
I/O
Function Block 3
I/O - Global Clocks
3
I/O - Global Set/Reset
1
Function Block n
I/O - Global Tri-States
2 or 4
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XC9500 Function Block

• Flexible 36V18 PAL Blocks

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XC9500 Macrocell
to/from other macrocells
From FastCONNECT
SUM-Term Logic
18
36
Register
XOR
D/T
Q
P-Term Allocator
P-term Clk
R
S
P-term RS
P-term OE
2 or 4
to/from other macrocells
3
Global Clocks
Global OEs
Global R/S
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HardWire

• Unique no-risk mask-programmed cost reduction
• Low cost at large volumes
• Savings of 40 to 70
• Architecture-equivalent mask-programmed version
  of any FPGA
• Requires virtually no customer engineering
  resources
• No resimulation
• Xilinx generates test vectors for 100 coverage

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Naming Conventions

• Xilinx Component naming convention Part name -
  speed- package. Example

XC4028XL-3-BG256
Package
Speed Grade
Sub-family (3V Xl or L, no XL or L 5V)
Maximum number of gates (thousands)
Family (XC4000, XC9500, XCS) S Spartan
The speed grade is a relative measure of internal
delay. Smaller numbers mean faster parts for all
families EXCEPT Spartan. For Spartan and all
future devices, larger numbers mean faster parts.