07 Input Output

1
Chapter 7

• Interupts
• DMA
• Channels
• Context Switching

2
Program Model Interrupt Model
Command Device
Done outside of user Program
Probably Hardware
Wait for Device Ready
Service Device OS Supplied ?
Service Device Programmer supplied
Probably Hardware
Interrupt Model
Program Model
3
Interrupt Physical Model

• CPU
• General Purpose Registers
• Program counter (PC)
• Stack Pointer (SP)
• User stack Pointer Storage
• Supervisor Stack Pointer Storage
• Program Status Word (PSW) Includes
• State user/supervisor, priority, etc.
• Program Priority
• Condition Codes (CC)
• Hardware to communicate over the BUS
• Address, Data, and Data Control
• Bus status and control
• Memory
• User program
• Interrupt Service Routine Program
• Operating System
• Interrupt Vector Table

4
Interface Registers

• Keyboard Device
• Keyboard Status Register (16 bit)
• Bit 15 Done Bit
• Bit 14 Interrupt Enable Bit
• Bits 0-2 Priority
• Keyboard Data Register (16 bit)
• Contains character entered
• Keyboard Interrupt Vector (16 bit)
• Contains the address in
  the Interrupt Vector Table
• Display Device
• Display Status Register (16 bit)
• Bit 15 Ready Bit
• Bit 14 Interrupt Enable Bit
• Bits 0-2 Priority

5
Interrupt Sequence

• Programmer Action
• Enable Interrupts by setting intr
  enable bit in Device Status Reg
• Enabling Mechanism for device
• When device wants service, and its
  enable bit is set
• (i.e, the I/O device has
  the right to request service), and
• the device priority is
  higher than the priority of the presently running
  program, and
• execution of an instruction is
  complete, then
• Process to Service the Interrupt
• The Processor saves the state of the
  program (must be able to return to program)
• The Processor goes into Privileged (or
  Supervisor) Mode
• The Priority level is set (established by the
  interrupting device)
• The context is switched
• The user SP is saved and the Supervisor SP
  loaded
• The (PC) and the (PSR) are PUSHED onto the
  Supervisor Stack
• The contents of the other registers are
  not saved. Why?
• The CCs are cleared. Why?

6
Interrupt Context Switching

• User Stack
• What goes on here
• Supervisor Stack
• PC
• SP
• PSW
• What about IR, GP Reg ?

What about the PSW, PC, GP Reg in the
Supervisor? Is the Interrupt Service Program run
in User or Supervisor mode? Who can write an
Interrupt service routine?
7
Alternatives for transferring Blocks of Data
to/from an I/O device

• Transfer can occur under program control
  perhaps with a subroutine (?)
• Transfer can occur with an Interrupt Service
  Routine requires context switch
• Transfer can occur with Direct Memory Access
  (DMA) In parallel or Pseudo Parallel of the
  Program/CPU

8
DMA Function

• Normally, the CPU is the only controller of the
  BUS
• Reads / Writes of Data to memory
• Read/Writes of Data/Status to I/O Devices
• DMA controller(s) takes over Bus control from CPU
  for I/O
• - Requires permission from Bus Controller
  (usually the CPU)
• Suspends the CPU while it reads/writes data, or
• Cycle steals uses BUS when it is not going
  to be utilized
• allowing the CPU to
  continue working
• (Note this is
  different from Stallings definition)
• Can read/write one word per DMA or
• a whole Block
• - Gives BUS back when finished
• - Typically interrupts the CPU when DMA is
  complete
• DMA requires an additional Module(s) attached to
  bus to provide BUS supervision when it is in
  control

9
Typical DMA Module Organization
/ Buffer
10
DMA Operation (Block Transfer)

• CPU provides direction to DMA controller(s)
• Like
• Read/Write
• Device address (which device)
• Starting address of memory block for data
• Amount of data to be transferred
• Mode(s) of data transfer
• When transfer begins, CPU is likely goes to sleep
• DMA controller deals with transfer (is BUS
  controller)
• DMA controller releases the BUS
• DMA controller sends an interrupt after finished
• What about context switching ?

11
DMA and Interrupt Breakpoints During an
Instruction Cycle
12
DMA Transfer - Cycle Stealing

• CPU provides direction to DMA controller(s)
• DMA controller provides bus control for a
  read/write cycle when the BUS is not being used
  How does it know?
• Transfers one word of data per cycle steal
• Data Transfer is slower than Block Transfer DMA,
  but faster than program control or using an
  interrupt service routine Why?
• Slows done the CPU/program very little Why ?

13
Cycle Stealing Options

• Stealing cycles when they arent going to be used
  anyway
• when an instruction is not going to use the bus
• when the cache is providing data
• when a partition of memory is not likely to be
  accessed

14
Several questions

• What effect does caching memory have on DMA?
• What effect does use of DRAMs have on DMA ?

15
DMA Configurations (1)

• Single Bus, Detached DMA controller
• Each transfer uses bus twice
• I/O to DMA then
• DMA to memory
• CPU is suspended twice

16
DMA Configurations (2)

• Single Bus, Integrated DMA controller
• Controller may support gt1 device
• Each transfer uses bus once
• DMA to memory
• CPU may be suspended only once

17
DMA Configurations (3)

• Separate I/O Bus
• Bus supports all DMA enabled devices
• Each transfer uses bus once
• DMA to memory
• CPU is suspended once

18
I/O Channels

• Used on large systems systems with many devices
• -
  especially many fast devices
• I/O channels are processors (programmable)
  dedicated to I/O
• CPU instructs I/O controller to do transfer and
  provides it mode
• I/O controller does entire transfer from one or
  many devices
• Advantages
• Makes transfers less visible to CPU, spreads the
  complexity
• Can Improve speed
• Can improve device organization flexibility

19
I/O Channel Architectures

• Selector Channel
• For one fast device at a time
• Multiplexor Channel
• For a number of slower devices used
  simultaneously