Verilog Descriptions of Digital Systems

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Verilog Descriptions of Digital Systems
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Design Flow
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Verilog Lab 3
  Design a serial adder circuit using Verilog. 
The circuit should add two 8-bit numbers, A and
B.  The result should be stored back into the A
register.  Use the diagram below to guide you. 
  Hint  Write one module to describe the
datapath and a second module to describe the
control.  Annotate your simvision trace output
to demonstrate that the adder works correctly. 
Demonstrate by adding 45 to 10 in your
testbench.  
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Serial Adder Data Path
pinB
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Adder/Subtractor
// 4-bit full-adder (behavioral) module fa(sum,
co, a, b, ci) input 30 a, b input
ci output 30 sum output co
assign co, sum a (ci ? b b) ci
endmodule
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Serial Adder Control Logic
pinB
T0 if (!start) goto T0 T1 if (start) goto
T1 T2 if (clrA) A lt 0, B lt pinB, C lt 0 T3
A lt shr(A), B lt shr(B) T4 A lt shr(A), B
lt shr(B) T5 A lt shr(A), B lt shr(B) T6 A
lt shr(A), B lt shr(B), goto T0
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Controller and Datapath Modules
pinB
module serial_adder_datapath(sum, sout, pinB,
ctl, reset, clk) output 70 sum
output sout input sinB input
ctl input reset, clk
endmodule module serial_adder_control(ctl,
busy, start, clrA, reset, inv_clk) output
ctl output busy input
reset, start, inv_clk endmodule
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Three Techniques for Building Control Units

1. Classical FSM
2. One-Hot
3. Decode a Counter

T0 if (!start) goto T0 T1 if (start) goto
T1 T2 if (clrA) A lt 0, B lt pinB, C lt 0 T3
A lt shr(A), B lt shr(B) T4 A lt shr(A), B
lt shr(B) T5 A lt shr(A), B lt shr(B) T6 A
lt shr(A), B lt shr(B), goto T0
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Binary Multiplication
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Binary Multiplier
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ASM Chart
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Numerical Example
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Serial Multiplier (Verilog)
// multiplier module multiplier(S, clk, clr,
Bin, Qin, C, A, Q, P) input S, clk, clr
input 40 Bin, Qin output C
output 40 A, Q output 20 P //
system registers reg C reg 40
A, Q, B reg 20 P reg 10
pstate, nstate parameter T0 2'b00, T1
2'b01, T2 2'b10, T3 2'b11 // combinational
circuit wire Z assign Z P //
state register process for controller always
_at_(negedge clk or negedge clr) begin if
(clr) pstate lt T0 else pstate lt
nstate end
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Serial Multiplier (Continued)
// state transition process for controller
always _at_(S or Z or pstate) begin case
(pstate) T0 if (S) nstate T1
else nstate T0 T1 nstate T2
T2 nstate T3 T3
if (Z) nstate T0 else nstate T2
endcase end // register transfer
operations always _at_(posedge clk) begin
case (pstate) T0 B lt Bin
T1 begin A lt 0
C lt 1 P
lt 5 Q lt Qin
end T2 begin
P lt P - 1 if (Q0)
C,A lt A B end
T3 begin C lt 0
A lt C, A41
Q lt A0, Q41 end
endcase end endmodule
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Serial Multiplier (Testbench)
// multiplier testbench module multiplier_tb
reg S, clk, clr reg 40 Bin, Qin
wire C wire 40 A, Q wire
20 P // instantiate multiplier
multiplier uut(S, clk, clr, Bin, Qin, C, A, Q,
P) // generate test vectors initial begin
0 begin S 0
clk 0 clr 0
end 5 begin S 1
clr 1 Bin 5'b10111
Qin 5'b10011 15 begin
S 0 end end
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Serial Multiplier (Testbench, continued)
// create dumpfile and generate clock initial
begin dumpfile("./multiplier.dmp")
dumpflush dumpvars(2,
multiplier_tb) repeat (26) 5 clk
clk end endmodule