EE 360M Digital Systems Design Using VHDL Lecture 3

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EE 360M - Digital Systems Design Using
VHDLLecture 3

• Nur A. Touba
• University of Texas at Austin

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DIGITAL DESIGN FLOW
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DESIGN ENTRY

• Schematic Capture
• Graphical Entry
• Use Standard Digital Building Blocks
• Gates, Flip-Flops, Decoders, Counters, etc.
• Hardware Description Languages (HDLs)
• E.g., VHDL, Verilog
• Behavioral Description Algorithmic Level
• C A B
• Structural Description Component Level
• Describe Interconnection of Gates in Adder
• Textual Description of Schematic

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HARDWARE DESCRITION LANGUAGES

• VHDL VHSIC Hardware Description Language
• VHSIC Very High Speed Integrated Circuit
• Originally Developed Under Funding from DoD
• Provide Uniform Method for Specifying Digital
  Systems
• Original Purpose to Describe and Document
• Not Synthesizing Hardware
• Syntactic Roots in ADA (also sponsored by DoD)
• Verilog
• Developed by Industry Around Same Time as VHDL
• Syntactic Roots in C

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VHDL SYNTAX

• Reserved Words
• Cannot Be Used as Identifiers
• Book/Notes Will Show in Bold Text
• Indentifiers
• Can Include Letters, Numbers, and Underscore _
• Must Begin with Letter and Cannot End with
  Underscore
• Generally Not Case Sensitive
• All Statements End with Semicolon
• Statements Can Wrap Around Multiple Lines
• Anything After - - in Line Treated as Comment

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SIMPLE GATE CIRCUIT
C lt A and B after 5 ns E lt C or D after 5 ns
What if order of statements reversed as follows?
E lt C or D after 5 ns C lt A and B after 5 ns
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INVERTER WITH FEEDBACK
CLK lt not CLK after 10 ns
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DIFFERENT DELAY GATES WITH COMMON INPUT
-- when A changes, these concurrent --
statements all execute at same time D lt A and B
after 2 ns E lt not A after 1 ns F lt A or C
after 3 ns
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BIT-VECTORS
B in bit_vector (3 downto 0) B lt 1100--
Assigns 1 to B(3), 1 to B(2), 0 to B(1),
and 0 to B(0)
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ARRAY OF AND GATES
-- hard wayC(3) lt A(3) and B(3)C(2) lt A(2)
and B(2)C(1) lt A(1) and B(1)C(0) lt A(0) and
B(0)
-- easy way-- assuming A,B,C 4-bit bit-vectors
C lt A and B
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VHDL MODULE WITH 2 GATES
entity two_gates is port (A,B,D in bit E
out bit)end two_gatesarchitecture gates of
two_gates is signal C bitbegin C lt A
and B -- concurrent E lt C or D --
statementsend gates
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BLACK BOX VIEW
entity entity-name is port (interface-signal
declaration) end entity entity-name
interface-signal declaration has following
form list-of-interface-signals mode type
initial value list-of-interface-signals
mode type initial value
port(A, B in integer 2 C, D out bit)
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MODE

• Mode indicates direction of information
• 5 Possible Modes in VHDL
• in only used as input
• out only used as output
• inout used both as input and output
• buffer used as output externally, but both
  input and output internally
• linkage used when VHDL entities connected to
  non-VHDL entities

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VHDL PROGRAM STRUCTURE
architecture architecture-name of entity-name is
declarations begin architecture body end
architecture architecture-name
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ENTITY DECLARATION FOR FULL ADDER
entity FullAdder is port (X,Y,Cin in bit
--Inputs Cout, Sum out bit)
--Outputsend FullAdder
architecture Equations of FullAdder isbegin --
concurrent assignment statements Sum lt X xor
Y xor Cin after 10 ns Cout lt (X and Y) or
(X and Cin) or (Y and Cin) after 10 ns end
Equations
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4-BIT ADDER
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4-BIT ADDER
entity Adder4 is port (A, B in bit_vector(3
downto 0) Ci in bit -- Inputs S
out bit_vector(3 downto 0) Co out bit) --
Outputsend Adder4 architecture Structure of
Adder4 iscomponent FullAdder port (X, Y,
Cin in bit -- Inputs Cout, Sum out
bit) -- Outputsend component signal C
bit_vector(3 downto 1) -- C is internal
signalbegin -- instantiate four copies of
FullAdder FA0 FullAdder port map (A(0),
B(0), Ci, C(1), S(0)) FA1 FullAdder port
map (A(1), B(1), C(1), C(2), S(1)) FA2
FullAdder port map (A(2), B(2), C(2), C(3),
S(2)) FA3 FullAdder port map (A(3), B(3),
C(3), Co, S(3))end Structure
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COMPONENT

• Component Declaration
• Component Instantiation

component component-name port
(list-of-interface-signals-and-their types) end
component
label component-name port map (list-of-actual-sig
nals)
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WHAT IS WRONG WITH THIS CODE?

• Will Not Compile or Simulate

entity gates is port (A, B, C in bit D, E
out bit) end gates   architecture example of
gates is begin D lt A or B after 5 ns --
statement 1 E lt C or D after 5 ns --
statement 2 end example
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VHDL PROCESS
process (sensitivity-list) begin sequential
statements end process
process (A, B, C, D) begin C lt A and B --
sequential E lt C or D -- statements end
process
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COMBINATIONAL LOGIC IN PROCESS

• Can Model Both Comb. and Seq. Logic in Process
• Need to be Very Careful with Combinational Logic

entity no_gates is port (A,B,C in bit D
buffer bit E out bit)end no_gatesarchitecture
behave of no_gates isbegin process (A, B,
C) begin D lt A or B after 5 ns --
statement 1 E lt C or D after 5 ns --
statement 2 end processend gates
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VHDL CODE FOR SIMPLE D FLIP-FLOP
process (CLK) begin if CLK'event and CLK
'1' -- rising edge of CLK then Q lt
D end if end process
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VHDL CODE FOR TRANSPARENT LATCH
process (G,D) begin if G '1' then Q lt D
end if end process
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D FLIP-FLOP WITH ASYNCHRONOUS CLEAR
process (CLK, ClrN) begin if ClrN '0' then
Q lt '0' else if CLK'event and CLK '1'
then Q lt D end if end
if end process

• For Simulation Purposes, One Could Use if CLK
  1
• Still Get Action Corresponding to Rising Edge
• However, for Synthesis Would Result in Latch

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EQUIVALENT USE OF NESTED IF AND ELSEIF
if (C1) then S1 S2 else if (C2) then S3
S4 else if (C3) then S5 S6
else S7 S8 end if end if end if
if (C1) then S1 S2 elsif (C2) then S3 S4
elsif (C3) then S5 S6 else S7 S8 end
if
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J-K FLIP-FLOP WITH DIRECT SET AND CLEAR
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entity JKFF is port (SN, RN, J, K, CLK in
bit -- inputs Q, QN out bit) end
JKFF architecture JKFF1 of JKFF is signal Qint
bit -- Qint can be used as input or
output begin Q lt Qint -- output Q and QN
to port QN lt not Qint -- combinational
output outside process process (SN, RN,
CLK) begin if RN '0' then Qint lt
'0' after 8 ns -- RN'0' will clear FF
elsif SN '0' then Qint lt '1' after 8 ns
-- SN'0' will set FF elsif CLK'event and
CLK '0' then -- falling edge of CLK
Qint lt (J and not Qint) or (not K and
Qint) after 10 ns end if end
process end JKFF1
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WAIT STATEMENTS
process begin sequential-statements
wait-statement sequential-statements
wait-statement . . . end process
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WAIT STATEMENTS

• Three Forms
• wait on sensitivity-list
• wait for time-expression
• wait until boolean-expression
• Examples

wait on A, B, C wait for 5 ns wait until A B
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WAIT STATEMENTS

• Process Must Use Either Sensitivity List or Wait
  Statements (Cannot Use Both)
• These are Equivalent

process (A,B,C,D) begin C lt A and B after 5
ns E lt C or D after 5 ns end process
process begin C lt A and B after 5 ns E
lt C or D after 5 ns wait on A, B, C, D end
process
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STATEMENT ORDER VERSUS SIGNAL UPDATE
process begin wait until clk'event and clk
'1' A lt E after 10 ns -- (1) B lt F
after 5 ns -- (2) C lt G -- (3) D lt H
after 5 ns -- (4) end process
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MULTIPLE STATEMENTS UPDATING SIGNAL
process (CLK) begin if CLK'event and CLK
'0' then Q lt A Q lt B Q lt C end
if end process
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WILL NOT SIMULATE
entity gates is port (A, B,C in bit D, E
out bit) end gates   architecture exam of gates
is begin process begin D lt A or
B after 2 ns E lt not C and A end
process end exam