ASIC 120: Digital Systems and Standard-Cell ASIC Design

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ASIC 120 Digital Systems and Standard-Cell ASIC
Design

• Tutorial 1 Introduction to Digital Circuits
• January 25, 2006

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Outline

• Digital Systems
• Digital Design and its relation to ASICs
• Combinational Logic
• NOT, AND, OR, XOR, NAND, etc.
• mux, half-adder, full-adder
• Sequential Logic
• flip-flop/register, shift register, counter

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Digital Systems

• Analog vs. Digital
• continuously varying vs. discrete
• imprecise vs. precise
• 0..1 vs. 0 or 1
• Digital systems excel at
• repetitive calculations
• large amounts of data
• reproducible results

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Digital Systems

• Implemented in integrated circuits (ICs) mounted
  on a printed circuit board (PCB)

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The Big Picture
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The Big Picture
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Components of a Digital System

• Printed circuit board (PCB)
• Embedded software
• microprocessor
• microcontroller
• digital signal processor (DSP)
• ASIC
• Programmable Logic Device (PLD)
• FPGA, etc.

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ASICs

• Application Specific Integrated Circuit
• from a user perspective, implies integrated
  circuit with a specific application
• from a design perspective, implies any integrated
  circuit
• Since we are designers, ASICs include
• SRAMs
• phase locked loops (PLLs)
• microprocessors
• analog-to-digital converters
• FPGAs
• etc.

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Consider an ASIC

• Physically comprised of
• Package
• Pins
• Silicon wafer
• metal interconnect layers
• insulating layers
• vias
• at the bottom, transistors resting on a silicon
  substrate

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Consider an ASIC Package
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Consider an ASIC Side View
Source Figure 3-11 from ECE 438 textbook
(Rabaey, Jan M., Anantha Chandrakasan, Borivoje
Nikolic, Digital Integrated Circuits A Design
Perspective, 2nd Edition Pearson Education New
Jersey, 2003.)
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Consider an ASIC Substrate
Source Figure 3-13 from ECE 438 textbook (Rabaey
et al., Digital Integrated Circuits, 2nd
Edition)
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Consider an ASIC

• Conceptually
• System
• Module
• Gate
• Circuit
• Device

Source Figure 1-6 from ECE 438 textbook (Rabaey
et al., Digital Integrated Circuits, 2nd
Edition)
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FPGAs

• Field Programmable Gate Array
• part of the Complex Programmable Logic Device
  (CPLD) family of PLDs
• essentially reprogrammable hardware
• FPGAs can be very small or very big
• clock rates over 1 GHz
• implement multiple 32-bit processors

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Components of an FPGA

• Logic Elements (LEs)
• Routing
• Input/Output logic
• Extra features
• clocking
• memory
• memory interfaces
• multipliers

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The Logic Element

• Two main parts
• Look-Up Table (LUT) for combinational logic
• Flip Flop (FF) for sequential logic (memory)

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Top Level View of an FPGA
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Top Level View of an FPGA
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Digital ASIC/FPGA Design Flow

• Dependent on target environment, process,
  resources available, etc.
• Generic flow
• System architecture
• Register Transfer Level (RTL)
• high level, synthesizable, optimized
• functional simulation, timing simulation
• Synthesis
• more simulation
• Manufacturing
• testing

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Register Transfer Level (RTL)

• This is where we start
• schematic
• hardware description languages (VHDL, etc.)

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Combinational and Sequential Logic

• We can break a digital system into two types of
  logic
• Combinational
• computation happens in a linear fashion
• Sequential
• computation involves a feedback loop (memory)

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RTL and Combinational/Sequential Logic
Sequential
Feedback
Data Out
Register
Register
Register
Data In
Cloud of Logic
Cloud of Logic
Clock
Combinational
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Combinational Logic NOT
Truth Table
Input
Output
A X
0 1
1 0
Boolean algebra expression X A
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Combinational Logic AND
A B X
0 0 0
0 1 0
1 0 0
1 1 1
Boolean algebra expressions X A ? B X AB
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Combinational Logic OR
A B X
0 0 0
0 1 1
1 0 1
1 1 1
Boolean algebra expression X A B
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Combinational Logic XOR
A B X
0 0 0
0 1 1
1 0 1
1 1 0
Boolean algebra expression X A ? B
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Combinational Logic NAND
A B X
0 0 1
0 1 1
1 0 1
1 1 0
Boolean algebra expressions X A ? B X AB
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NAND Transistor Schematic
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NAND Transistor Layout
vdd
gnd
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Combinational Logic NOR, XNOR
A B X
0 0 1
0 1 0
1 0 0
1 1 0
X A B
A B X
0 0 1
0 1 0
1 0 0
1 1 1
X A ? B
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Building Combinational Circuits
A B C X
0 0 0 0
0 1 0 0
1 0 0 1
1 1 0 1
0 0 1 0
0 1 1 1
1 0 1 0
1 1 1 1
X AC BC
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Combinational Logic MUX(multiplexer)
A B C X
0 0 0 0
0 1 0 0
1 0 0 1
1 1 0 1
0 0 1 0
0 1 1 1
1 0 1 0
1 1 1 1
X AC BC
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Half Adder
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
S A ? B C AB
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Full Adder
S A ? B ? Ci Co AB Ci(A ? B)
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Full Adder
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Full Adder Application 8-BitRipple-Carry Adder

• Constructed by connecting 8 full adders together

A0
A1
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
0
Carry Out
S0
S1
S2
S3
S4
S5
S6
S7
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What Ive Skipped

• Gates with more than two inputs
• Karnaugh maps
• Quine-McCluskey method
• Binary arithmetic, base conversions
• Practical digital circuits have more than 0s and
  1s
• Transmission gates, tri-state buffers

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Sequential Logic
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Basic Feedback Element SR Latch
S R Q Qnext
0 0 0 0
0 0 1 1
1 0 1 1
1 0 0 1
0 1 1 0
0 1 0 0
1 1 0 N/A
1 1 1 N/A
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Basic Feedback Element SR Latch

• Simplified truth table

S R Q
0 0 hold
1 0 1 (set)
0 1 0 (reset)
1 1 invalid
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Basic Feedback Element SR Latch
0
0
1
0
(Hold State)
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Basic Feedback Element SR Latch
0
0
1
0
1
0
(Hold State)
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Basic Feedback Element SR Latch
0
1
0
0
(Hold State)
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Basic Feedback Element SR Latch
0
1
0
1
0
0
(Hold State)
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Basic Feedback Element SR Latch
0
0
1
1
(Set State)
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Basic Feedback Element SR Latch
0
0
1
0
1
1
(Set State)
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Basic Feedback Element SR Latch
0
0
1
0
0
1
(Set State)
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Basic Feedback Element SR Latch
0
0
0
0
0
1
(Set State)
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Basic Feedback Element SR Latch
0
1
0
0
0
1
(Set State)
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Basic Feedback Element SR Latch
0
1
0
1
0
1
(Set State)
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Basic Feedback Element SR Latch
1
0
1
1
(Invalid State)
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Basic Feedback Element SR Latch
1
0
1
0
1
1
(Invalid State)
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Basic Feedback Element SR Latch
1
0
1
0
0
1
(Invalid State)
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Basic Feedback Element SR Latch
1
0
0
0
0
1
(Invalid State)
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Basic Feedback Element SR Latch

• Q and Q are supposed to have opposite
  (complementary) values
• i.e., Q Q
• In the invalid state (S 1, R 1) Q ? Q
• should be avoided

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D Flip-Flop or Register
D Clk Q Qnext
0 0 0 0
0 0 1 1
1 0 0 0
1 0 1 1
0 0?1 0 0
0 0?1 1 0
1 0?1 0 1
1 0?1 1 1
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D Flip-Flop or Register

• Clock input controls when data output takes value
  of data input
• triggered on either rising or falling edge of
  clock

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Latches vs. Flip-Flops

• Latches
• no clock input
• data output changes in response to data input
• level-sensitive
• Flip-Flops
• has clock input
• data output changes in response to data input on
  rising or falling clock edge
• edge-sensitive

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Synchronous vs. Asynchronous

• Synchronous
• circuit operation governed by a clock
• currently more popular and practical
• flip-flops
• Asynchronous
• circuit operation independent of a clock
• potentially faster than synchronous
• lower power consumption
• difficult to design
• latches

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Sequential Constructs

• Shift registers
• Counters
• State Machines (next tutorial)

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Shift Register

• Consider a series of D flip-flops (DFFs)
  connected in series, as a 4-bit shift register

Data Out
Data In
Clk
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Shift Register
0
0
0
0
0
Data Out
Data In
0
Clk
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Shift Register
0
0
1
0
0
Data Out
Data In
0
Clk
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Shift Register
0
0
1
1
0
Data Out
Data In
? (1)
Clk
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Shift Register
0
0
0
1
0
Data Out
Data In
? (0)
Clk
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Shift Register
0
0
0
0
1
Data Out
Data In
? (1)
Clk
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Shift Register
1
0
0
0
0
Data Out
Data In
? (1)
Clk
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Shift Register
0
1
0
0
0
Data Out
Data In
? (1)
Clk
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Counters Ring Counter

• Connect shift register output to input
• Add set and clear functionality to DFFs

Clk
Init
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Counters Ring Counter
0
0
0
1
0
Clk
1
Init
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Counters Ring Counter
0
0
0
1
0
Clk
0
Init
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Counters Ring Counter
0
0
0
0
1
? (1)
Clk
0
Init
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Counters Ring Counter
1
0
0
0
0
? (1)
Clk
0
Init
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Counters Ring Counter
0
1
1
0
0
? (1)
Clk
0
Init
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Counters Ring Counter

• Each DFF output is a digit in a binary number
• Sequence was 1000 (8)
• 0100 (4)
• 0010 (2)
• 0001 (1)
• 1000 (8)

0
0
0
1
0
? (1)
Clk
0
Init
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T Flip-Flop

• Clock is the only input
• Output inverts on rising edge of the clock (or
  toggle) input

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Counters Binary Counter

• Implemented using series of T flip-flops
• Counts 0000, 0001, 0010, 0011, etc.

Clk
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Counters Binary Counter
0
0
0
0
Clk
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Counters Binary Counter
0
0
1
0
? (1)
Clk
80
Counters Binary Counter
0
0
0
1
? (1)
Clk
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Counters Binary Counter
0
0
1
1
? (1)
Clk
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Counters Binary Counter
1
0
0
0
? (1)
Clk
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Counters Binary Counter
and so on
1
0
1
0
Q
Q
Q
Q
? (1)
Clk
T
T
T
T
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State Machines

• Useful abstract constructs for more complex
  sequential logic
• More on these next time

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What Ive Skipped

• Other flip-flops (RS, JK)
• Many other interesting sequential circuits
  (barrel shifters, gray counters, etc.)

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Hardware Description Languages (HDLs)

• HDL describes in text a digital circuit
• Examples
• VHDL (we will look at this next time)
• Verilog
• AHDL
• JHDL

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Hardware Description Languages (HDLs)

• schematics are useful for
• drawing high level diagrams
• manually working out simple pieces of logic
• HDLs are useful for
• describing complex digital systems
• HDLs are not...
• software programming languages (C, Java,
  assembly, etc.)

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Summary

• Digital Systems
• Digital Design and its relation to ASICs
• Combinational Logic
• NOT, AND, OR, XOR, NAND, etc.
• mux, half-adder, full-adder
• Sequential Logic
• flip-flop/register, shift register, counter

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Next Tutorial

• State machines
• Tutorial 1 in VHDL
• Digital Design Thought Process
• VHDL is not a programming language like C or Java
• hardware entities represented using text

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UW ASIC Design Team

• www.asic.uwaterloo.ca
• Reference material
• Bryce Leungs tutorials (UW ASIC website)
• Michael Goldsmiths tutorials (UW ASIC website)
• ECE 223, 427, 438 course notes textbooks
• My contact info
• Jeff Wentworth, j.wentworth_at_gmail.com