MOS Field-Effect Transistors

1
MOS Field-Effect Transistors for High-Speed
Operation
Day 4A, May 30, 2008, Pisa
2
Si MOSFET features

• 4 terminals
• 2D-device
• "The most abundant object made by mankind"

3
NP-junctions and transistor action
HBT, BJT
MOSFET
B
G
Cox
RB
E
D
S
CsdQs/dVaj
C
Rj
x0
x0
What happens ?
4
Transistor transfer characteristics
BJT E/B 1E19/1E17
MOSFET S/B 1E20/8E17
Vbi
ON
Getting HOT
"OFF" Sub-threshold
ON
Note relative "linearities" and current ranges
5
SUB-THRESHOLD CONDITION (DEPLETION)

• Depletion layer forms

6
ON CONDITION (Strong Inversion)
-

VDS

• Inversion layer forms

-

VGS
iG


iD
iS
-
-
-
x
VSB
iB
7
Decomposing the MOSFET
1. Ignore S and D 2. Take vertical section from G
? B
EC
y

• n poly gate
• work functions
• oxide electron affinity and Eg

Note
8
Equilibrating the MOSCAP
- electrons transfer, driven by difference in
EF - electrons recombine in body at the
interface - depletion layer forms - charge
separation creates field in oxide
Equilibration process
-Vfb
9
Surface potential and the PSP model
q?B
10
Introducing the channel potential
THE GRADUAL CHANNEL APPROXIMATION
11
Implicit expression for ?s
12
Varying degrees of inversion along the channel
13
The Drain Current
Charge Sheet Approximation Depletion
Approximation
DDE
IEEE convention
14
Drain I-V characteristics

• Diffusion in sub-threshold
• Drift in strongly ON

• Smooth curves !

15
Saturation and loss of inversion

• In Saturation
• Qn(L) becomes very small.
• Field lines from gate terminate on acceptors in
  body.
• Drain end of channel is NOT in strong inversion,
• but SPICE models assume that it is !

16
Development of SPICE Level 1 model
From PSP
Make strong-inversion assumptions
Use Binomial Expansion
Threshold voltage
17
Comparison of PSP and SPICE
VDS (V)
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Improving the SPICE model

• Increase ?s at strong inversion

19
SPICE Level 49 allowing for vsat
v ?E(x)
Combining the velocities
vvsat
Putting this together with GCA, CSM, dVCS(x)/dx
20
Comparison of SPICE Levels 1 and 49
21
Subthreshold current
From PSP
Weak inversion
Expand Qn and substitute in PSP Diffusion
Equation.
Convert ?s to VGS
Subthreshold current
22
Subthreshold current comparison
23
Si CMOS why is it dominant for digital?
4 reasons

1. "Low" OFF current.
2. Compact logic few transistors and no level
   shifting.
3. Small footprint.
4. Industrial investment.

IN
OUT
VSS
VDD
Example of small footprint
24
CMOS the Industrial drive
Nodes relate to the DRAM half pitch, i.e., the
width, and space in between, metal lines
connecting DRAM bit cells
25
Logic speed is about Q and I

• Need
• high ? - certainly
• Low L - but it adversely affects VT
• High Cox - but low CoxZL
• Low VDD - but it adversely affects ION
• Low VT - but it adversely affects ISUBT

26
3 major concerns for digital CMOS

1. Increasing ION via mobility improvement
2. Reducing gate leakage via thicker, high-k
   dielectrics
3. Controlling VT and Isubt via suppression of the
   short-channel effect

27
Improving ? direction-dependent m

• k1 is a lt100gt direction
• k2 and k3 are orthogonal at the point of the
  energy minimum EC

Which direction has the higher effective mass?
28
Conductivity effective mass mC
Electron accelerates in field E and reaches vd on
next collision after time ?
?
v 0
v vd
What happens when Si is biaxially tensioned?
For unstrained lt100gt Si mC 0.26m0
29
Effect of biaxial tensile strain on EC

• ?4 valleys raised in energy

• ?2 valleys lowered in energy

Unstrained
30
Strained Si at the 45nm node
31
High-k dielectrics

• High COX needed for ID and S
• High tOX needed to reduce gate leakage
• Resolve conflict by increasing ?

32
Tunneling through the oxide
Simplify the U profile ?
Solve SWE in each region
write as
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Solutions for ? ?
Physically what is the "D-wave" ?
What is ? ? ?
Why is it -oscillatory in the channel ? -
damped in the oxide ? - constant in the gate ?
y (m)
34
Transmission Probability Definition
3. Define the Transmission Probability
1. For the channel
2. Do the derivatives and the conjugates
What is the interpretation of this ?
What do these mean ?
35
Silica, hafnia, and electron affinity
36
Tunneling current
100 improvement in Cox
50 improvement in Cox
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The Short-Channel Effect
?s f (L, VDS)
? VT f (L, VDS)
?s is determined by capacitive coupling via Cox
and Cbody, AND by capacitive coupling via CDS
38
Reduce CDS by shrinking yj
It's like reducing the area of a parallel plate
capacitor
yj
39
SCE on Drain Current
40
Reduce CDS by screening Ex
41
Using SOI to beat SCE
Alvin Loke
Daryl Van Vorst