Chapter 12 Field-Effect Transistors ?????

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Chapter 12Field-Effect Transistors ?????
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Field-Effect Transistors (FETs)

• FET (?????) ?????????????,???????????????,????????
  ? ?
• Metal-Oxide-Semiconductor Field-Effect Transistor
  (MOSFET,????????)???NMOS (????????)?PMOS(????????)
  ?
• MOSFET ??source (??)?gate (??)?drain(??)?body(??)
  ?

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12.1 NMOS AND PMOS TRANSISTORS
NMOS Transistor (n-p-n)
???????,??? ??????? ?????????? ????????
(gate ??)
(drain ??)
(source ??)
(O, ?)
(M, ?)
??
(S, ?)
(Body ??)
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NMOS (n-channel MOS)

• NMOS ? source (??)?drain(??)?n-type ???, body(??)
  ?p-type ???, gate (??)??? ?

n-p-n
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NMOS ??? (Operation)

• NMOS ????????(region)
• Cutoff Region (???)
• Triode Region (???) or Linear Region (???)
• Saturation Region (???)

and
and
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Operation in the Cutoff Region

• ???(gate)???(source)???vGS 0,??pn??(body-source)
  ?(body-drain)?????????????,??MOSFET???(cutoff)?
• ???(gate)???(source)???vGS ?????gtVto (threshold
  voltage,????)?,?NMOS???????

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Operation in the Triode Region
and

• ???(gate)????,??????????????????, ????????????

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Operation in the Triode Region
and

• ???(gate)???(source)???vGS ?????gtVto (threshold
  voltage,????),??drain?source??????vDS,???n-type??(
  channel),?????????????????,??????(drain
  current)iD,????drain??source,?????????????
• ?vDS???, iD?vDS???, ??vGS - Vto????
• ????????,????? iG 0?

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Operation in the Triode Region

• In the triode region, the NMOS behaves as a
  resistor connected between drain and source, but
  the resistance decreases as vGS increases.

0, if vDS0
Device parameter
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Operation in the Saturation Region
and

• ?drain?source????vDS vGS - Vto(or vGD Vto)
  ?n-type???drain?????0 ,vDS???, iD????, ??????

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Operation in the Saturation Region
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Boundary between Triode and Saturation Regions
At boundary, ??n-type???drain??????0
??I-V equation in saturation region
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Boundary between Triode and Saturation Regions
? ??I-V
equation in triode region
???????
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boundary
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Example 12.1
A NMOS transistor W160um, L2um, KP50uA/V2, and
Vto2 V. Plot the drain characteristic curves to
scale for vGS0, 1,2, 3, 4, and 5 V.
1. ? K
2. ? boundary
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3. ? saturation currents
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4. Plot characteristics in the triode region
(parabola ???).
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PMOS

• PMOS ? source ?drain?p-type ???, body?n-type ???,
  gate (??)??? ?
• ?????????

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MOSFET Summary
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12.2 LOAD-LINE ANALYSIS OF A SIMPLE NMOS
AMPLIFIER
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12.2 LOAD-LINE ANALYSIS OF A SIMPLE NMOS
AMPLIFIER

• VGG (dc source) ?NMOS ????(bias) ,?????, ?ac
  input ???????????,??vGS, iD???????

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• iD?????,??RD??????????, ??vDS?? ac output?

KVL
Load-line equation
Load-line ???
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• Quiescent operation point (Q point) is at vin0.

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1 V
VGSQ4
5 V
VDQ11
7 V
Distortion (??)
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Distortion
Distortion is due to that the characteristic
curves for the FET are not uniformly spaced. If a
much smaller input amplitude was applied we would
have amplification without appreciable distortion.
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Amplifier Analysis
12.3 Bias Circuits
Amplifier analysis has two steps 1. Determine
the Q point. 2. Use a small-signal equivalent
circuit to determine impedances and gains.
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The Fixed- Plus Self-Bias Circuit
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The Fixed- Plus Self-Bias Circuit
1. Thévenin equivalent
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2. KVL
3. Usually, transistor operates in saturation
region
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4. Load Line Analysis iD vs. vGS
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5. Determine vDS
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Example 12.2
Analyze the following circuit. The transistor
KP50uA/V2, Vto2 V, L10um, W400um
1. Determine K
2. Thévenin equivalent
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3. Determine VGSQ

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4. IDQ VDSQ
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12.4 SMALL-SIGNAL EQUIVALENT CIRCUITS
Small signal (ac)
Small signal (ac)
To determine vgs(t) vs. id(t)
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SMALL-SIGNAL EQUIVALENT CIRCUITS
At Q point
0