Registers

1
Registers

• CPE 49
• RMUTI
• KOTAT

2
Shift Registers

• Capability to shift bits
• In one or both directions
• Why?
• Part of standard CPU instruction set
• Cheap multiplication
• Serial communications
• Just a chain of flip-flops

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Simple 4-Bit Shift Register

• Clocked in common
• Just serial in and serial out
• Not quite a FIFO

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Serial In - Serial Out Shift Registers
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Serial In - Parallel Out Shift Registers
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Parallel In - Serial Out Shift Registers
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Parallel In - Parallel Out Shift Registers
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Bidirectional Shift Registers
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Shift Register Counters
Ring Counters
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Shift Register Counters
Johnson Counters
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Applications
To produce time delay The serial in -serial out
shift register can be used as a time delay
device.  The amount of delay can be controlled
by - the number of stages in the register -
the clock frequency To simplify combinational
logic The ring counter technique can be
effectively utilized to implement synchronous
sequential circuits.  A major problem in the
realization of sequential circuits is the
assignment of binary codes to the internal states
of the circuit in order to reduce the complexity
of circuits required.  By assigning one flip-flop
to one internal state, it is possible to simplify
the combinational logic required to realize the
complete sequential circuit.  When the circuit is
in a particular state, the flip-flop
corresponding to that state is set to HIGH and
all other flip-flops remain LOW.
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Applications
To convert serial data to parallel data A
computer or microprocessor-based system commonly
requires incoming data to be in parallel format.
 But frequently, these systems must communicate
with external devices that send or receive serial
data.  So, serial-to-parallel conversion is
required.  As shown in the previous sections, a
serial in - parallel out register can achieve
this.
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Symbol

• we could gate the clock

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Parallel Load

• Can provide parallel outputs from flip-flops
• And also parallel inputs

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Schematic
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Why is this useful?

• Basis for serial communications
• Keyboard
• Serial port
• Initially to connect to terminals
• Now mainly for modem

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Bidirectional Shift Register

• Shift either way
• Now we have following possible inputs
• Parallel load
• Shift from left
• Shift from right
• Also no change
• Schematic next

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Schematic
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Verilog for Shift Register

• module srg_4_r_v (CLK, RESET, SI, Q,SO)
• input CLK, RESET, SI
• output 30 Q
• output SO
• reg 30 Q
• assign SO Q3
• always_at_(posedge CLK or posedge RESET)
• begin
• if (RESET)
• Q lt 4'b0000
• else
• Q lt Q20, SI
• end
• endmodule

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Serial Transfer

• Parallel transfer over as many wires as word
  (for example)
• Serial transfer over a single wire
• Trade time for wires
• Takes n times longer

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Example
Why do this? Maybe these are far apart
Could shift data in
Whats on wire at each clock?
Clocked 4 times
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Table Showing Shift

• Hopefully weve figured it out

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Serial Addition
Initially reset all registers
Register A accumulates
At same time, new value going into B
Shift value in serially
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Hardware Comparison

• Serial vs. parallel adder
• One full adder vs. n adders
• Serial takes n units of time, parallel only one

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Arbitrary Count

• One more type of counter is useful
• Count an arbitrary sequence
• Maybe you need a sequence of states

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Circuit and State Diagram
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Shift Registers

• N-bit register with the provision for shifting
  its stored data by a bit position each tick of
  the clock.
• Serial input specifies a new bit to shifted
  into the register.
• Serial output specifies the bits being shifted
  out of the register

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References

• http//www.eelab.usyd.edu.au/digital_tutorial/part
  2/hpage.html
• http//www.allaboutcircuits.com/vol_4/index.html