Behavioral Design Style: Registers, Counters, Shift Registers

1
Behavioral Design Style Registers, Counters,
Shift Registers
ECE 448 Lecture 5
2
Required reading

• S. Brown and Z. Vranesic, Fundamentals of
  Digital Logic with VHDL Design
• Chapter 7, Flip-Flops, Registers, Counters,
• and a Simple Processor
• (7.14 optional)

3
Optional Reading

• Sundar Rajan, Essential VHDL RTL Synthesis
• Done Right
• Chapter 4, Registers and Latches
• Chapter 5, Counters and Simple Arithmetic
• Functions
• (see errata at http//www.vahana.com/bugs.ht
  m)

4
Behavioral Design Style Registers Counters
5
What is a PROCESS?

• A process is a sequence of instructions referred
  to as sequential statements.

The keyword PROCESS

• A process can be given a unique name using an
  optional LABEL
• This is followed by the keyword PROCESS
• The keyword BEGIN is used to indicate the start
  of the process
• All statements within the process are executed
  SEQUENTIALLY. Hence, the order of statements is
  important.
• A process must end with the keywords END PROCESS.

testing PROCESS BEGIN test_vectorlt00 WAI
T FOR 10 ns test_vectorlt01 WAIT FOR 10
ns test_vectorlt10 WAIT FOR 10
ns test_vectorlt11 WAIT FOR 10 ns END
PROCESS
6
Anatomy of a Process
OPTIONAL
label PROCESS (sensitivity list)
declaration part BEGIN statement part END
PROCESS label
7
Statement Part

• Contains Sequential Statements to be Executed
  Each Time the Process Is Activated
• Analogous to Conventional Programming Languages

8
PROCESS with a SENSITIVITY LIST

• List of signals to which the process is
  sensitive.
• Whenever there is an event on any of the signals
  in the sensitivity list, the process fires.
• Every time the process fires, it will run in its
  entirety.
• WAIT statements are NOT ALLOWED in a processes
  with SENSITIVITY LIST.

• label process (sensitivity list)
• declaration part
• begin
• statement part
• end process

9
Processes in VHDL

• Processes Describe Sequential Behavior
• Processes in VHDL Are Very Powerful Statements
• Allow to define an arbitrary behavior that may be
  difficult to represent by a real circuit
• Not every process can be synthesized
• Use Processes with Caution in the Code to Be
  Synthesized
• Use Processes Freely in Testbenches

10
Use of Processes in the Synthesizable Code
11
Component Equivalent of a Process
priority PROCESS (clk) BEGIN IF w(3) '1'
THEN y lt "11" ELSIF w(2) '1' THEN y
lt "10" ELSIF w(1) c THEN y lt a and
b ELSE z lt "00" END IF END PROCESS

• All signals which appear on the left of signal
  assignment statement (lt) are outputs e.g. y, z
• All signals which appear on the right of signal
  assignment statement (lt) or in logic expressions
  are inputs e.g. w, a, b, c
• All signals which appear in the sensitivity list
  are inputs e.g. clk
• Note that not all inputs need to be included in
  the sensitivity list

12
VHDL Design Styles
VHDL Design Styles
structural
behavioral
Components and interconnects
Concurrent statements
Sequential statements

• Registers
• Shift registers
• Counters
• State machines

synthesizable
and more if you are careful
13
Registers
14
D latch
Truth table
Graphical symbol
Q(t1)
Clock
D
Q(t)

0
0
1
0
1
1
1
Timing diagram
t
t
t
t
1
2
3
4
Clock
D
Q
Time
15
D flip-flop
Truth table
Graphical symbol
Q(t1)
Clk
D

0
?
0
1
?
1

Q(t)
0
Q(t)
1

Timing diagram
t
t
t
t
1
2
3
4
Clock
D
Q
Time
16
D latch
LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY latch IS PORT ( D, Clock IN
STD_LOGIC Q OUT STD_LOGIC) END
latch ARCHITECTURE Behavior OF latch IS
BEGIN PROCESS ( D, Clock ) BEGIN IF Clock
'1' THEN Q lt D END IF END PROCESS
END Behavior
17
D flip-flop
LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY flipflop IS PORT ( D, Clock
IN STD_LOGIC Q OUT STD_LOGIC) END
flipflop ARCHITECTURE Behavior_1 OF flipflop
IS BEGIN PROCESS ( Clock ) BEGIN IF
Clock'EVENT AND Clock '1' THEN Q lt D
END IF END PROCESS END Behavior_1
Q
D
Clock
18
D flip-flop
LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY flipflop IS PORT ( D, Clock
IN STD_LOGIC Q OUT STD_LOGIC) END
flipflop ARCHITECTURE Behavior_2 OF flipflop
IS BEGIN PROCESS BEGIN WAIT UNTIL
Clock'EVENT AND Clock '1' Q lt D END
PROCESS END Behavior_2
Q
D
Clock
19
D flip-flop with asynchronous reset
LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY flipflop IS PORT ( D, Resetn, Clock
IN STD_LOGIC Q OUT STD_LOGIC)
END flipflop ARCHITECTURE Behavior OF
flipflop IS BEGIN PROCESS ( Resetn, Clock )
BEGIN IF Resetn '0' THEN Q lt '0'
ELSIF Clock'EVENT AND Clock '1' THEN Q
lt D END IF END PROCESS END Behavior
Q
D
Clock
Resetn
20
D flip-flop with synchronous reset
LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY flipflop IS PORT ( D, Resetn, Clock
IN STD_LOGIC Q OUT STD_LOGIC)
END flipflop ARCHITECTURE Behavior OF
flipflop IS BEGIN PROCESS BEGIN WAIT
UNTIL Clock'EVENT AND Clock '1' IF Resetn
'0' THEN Q lt '0' ELSE Q lt D
END IF END PROCESS END Behavior
Q
D
Clock
Resetn
21
8-bit register with asynchronous reset
LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY reg8 IS PORT ( D IN
STD_LOGIC_VECTOR(7 DOWNTO 0) Resetn,
Clock IN STD_LOGIC Q OUT
STD_LOGIC_VECTOR(7 DOWNTO 0) ) END reg8
ARCHITECTURE Behavior OF reg8
IS BEGIN PROCESS ( Resetn, Clock ) BEGIN IF
Resetn '0' THEN Q lt "00000000" ELSIF
Clock'EVENT AND Clock '1' THEN Q lt D
END IF END PROCESS END Behavior
22
N-bit register with asynchronous reset
LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY regn IS GENERIC ( N INTEGER 16 )
PORT ( D IN STD_LOGIC_VECTOR(N-1 DOWNTO
0) Resetn, Clock IN STD_LOGIC Q
OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) END regn
ARCHITECTURE Behavior OF regn
IS BEGIN PROCESS ( Resetn, Clock ) BEGIN IF
Resetn '0' THEN Q lt (OTHERS gt '0')
ELSIF Clock'EVENT AND Clock '1' THEN Q
lt D END IF END PROCESS END Behavior
23
N-bit register with enable
LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY regn IS GENERIC ( N INTEGER 8 )
PORT ( D IN STD_LOGIC_VECTOR(N-1 DOWNTO
0) Enable, Clock IN STD_LOGIC Q
OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) END
regn ARCHITECTURE Behavior OF regn
IS BEGIN PROCESS (Clock) BEGIN IF
(Clock'EVENT AND Clock '1' ) THEN IF Enable
'1' THEN Q lt D END IF END
IF END PROCESS END Behavior
Enable
Q
D
Clock
regn
24
Counters
25
2-bit up-counter with synchronous reset
LIBRARY ieee USE ieee.std_logic_1164.all USE
ieee.std_logic_unsigned.all ENTITY upcount
IS PORT ( Clear, Clock IN STD_LOGIC Q
BUFFER STD_LOGIC_VECTOR(1 DOWNTO 0) ) END
upcount ARCHITECTURE Behavior OF upcount
IS BEGIN upcount PROCESS ( Clock ) BEGIN IF
(Clock'EVENT AND Clock '1') THEN IF Clear
'1' THEN Q lt "00" ELSE Q lt Q
01 END IF END IF END PROCESS END
Behavior
26
4-bit up-counter with asynchronous reset (1)
LIBRARY ieee USE ieee.std_logic_1164.all USE
ieee.std_logic_unsigned.all ENTITY upcount
IS PORT ( Clock, Resetn, Enable IN
STD_LOGIC Q OUT STD_LOGIC_VECTOR (3
DOWNTO 0)) END upcount
27
4-bit up-counter with asynchronous reset (2)
ARCHITECTURE Behavior OF upcount IS SIGNAL Count
STD_LOGIC_VECTOR (3 DOWNTO 0) BEGIN PROCESS
( Clock, Resetn ) BEGIN IF Resetn '0'
THEN Count lt "0000" ELSIF (Clock'EVENT
AND Clock '1') THEN IF Enable '1'
THEN Count lt Count 1 END IF END
IF END PROCESS Q lt Count END Behavior
28
Shift Registers
29
Shift register
Q(1)
Q(0)
Q(2)
Q(3)
Sin
Clock
Enable
30
Shift Register With Parallel Load
Load
D(3)
D(1)
D(2)
Sin
Clock
Enable
Q(0)
Q(1)
Q(2)
Q(3)
31
4-bit shift register with parallel load (1)
LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY shift4 IS PORT ( D IN
STD_LOGIC_VECTOR(3 DOWNTO 0) Enable IN
STD_LOGIC Load IN STD_LOGIC Sin
IN STD_LOGIC Clock IN STD_LOGIC Q
BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0) ) END
shift4
32
4-bit shift register with parallel load (2)
ARCHITECTURE Behavior_1 OF shift4
IS BEGIN PROCESS (Clock) BEGIN IF
Clock'EVENT AND Clock '1' THEN IF Load
'1' THEN Q lt D ELSIF Enable 1
THEN Q(0) lt Q(1) Q(1) lt Q(2)
Q(2) lt Q(3) Q(3) lt Sin END IF
END IF END PROCESS END Behavior_1
33
N-bit shift register with parallel load (1)
LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY shiftn IS GENERIC ( N INTEGER 8 )
PORT ( D IN STD_LOGIC_VECTOR(N-1 DOWNTO 0)
Enable IN STD_LOGIC Load IN
STD_LOGIC Sin IN STD_LOGIC Clock
IN STD_LOGIC Q BUFFER STD_LOGIC_VECTOR(N-1
DOWNTO 0) ) END shiftn
34
N-bit shift register with parallel load (2)
ARCHITECTURE Behavior OF shiftn
IS BEGIN PROCESS (Clock) BEGIN IF
(Clock'EVENT AND Clock '1' ) THEN IF Load
'1' THEN Q lt D ELSIF Enable 1
THEN Genbits FOR i IN 0 TO N-2
LOOP Q(i) lt Q(i1) END LOOP
Q(N-1) lt Sin END IF END IF END
PROCESS END Behavior
35
Generic ComponentInstantiation
36
N-bit register with enable
LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY regn IS GENERIC ( N INTEGER 8 )
PORT ( D IN STD_LOGIC_VECTOR(N-1 DOWNTO
0) Enable, Clock IN STD_LOGIC Q
OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) END
regn ARCHITECTURE Behavior OF regn
IS BEGIN PROCESS (Clock) BEGIN IF
(Clock'EVENT AND Clock '1' ) THEN IF Enable
'1' THEN Q lt D END IF END
IF END PROCESS END Behavior
Enable
Q
D
Clock
regn
37
Circuit built of medium scale components
s(0)
En
r(0)
p(0)
0
1
r(1)
q(0)
Enable
w
p(1)
w
y
0
y
0
0
z(0)
t(0)
0
q(1)
w
r(2)
1
w
y
p(2)
y
1
1
1
z(1)
t(1)
r(3)
w
ena
D
Q
2
y
z
w
2
z(2)
t(2)
3
priority
r(4)
p(3)
y
0
En
3
z(3)
t(3)
regn
dec2to4
1
r(5)
Clock
Clk
s(1)
38
Structural description example (1)

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• ENTITY priority_resolver IS
• PORT (r IN STD_LOGIC_VECTOR(5 DOWNTO 0)
• s IN STD_LOGIC_VECTOR(1 DOWNTO 0)
• clk IN
  STD_LOGIC
• en IN STD_LOGIC
• t OUT STD_LOGIC_VECTOR(3 DOWNTO 0) )
• END priority_resolver
• ARCHITECTURE structural OF priority_resolver IS
• SIGNAL p STD_LOGIC_VECTOR (3 DOWNTO 0)
• SIGNAL q STD_LOGIC_VECTOR (1 DOWNTO 0)
• SIGNAL z STD_LOGIC_VECTOR (3 DOWNTO 0)
• SIGNAL ena STD_LOGIC

39
Structural description example (2)
COMPONENT mux2to1 PORT (w0, w1, s
IN STD_LOGIC f OUT STD_LOGIC )
END COMPONENT COMPONENT priority PORT (w
IN STD_LOGIC_VECTOR(3 DOWNTO 0) y OUT
STD_LOGIC_VECTOR(1 DOWNTO 0) z OUT
STD_LOGIC ) END COMPONENT COMPONENT
dec2to4 PORT (w IN STD_LOGIC_VECTOR(1 DOWNTO
0) En IN STD_LOGIC y OUT
STD_LOGIC_VECTOR(3 DOWNTO 0) ) END COMPONENT
40
Structural description example (3)
COMPONENT regn GENERIC ( N INTEGER 8 )
PORT ( D IN STD_LOGIC_VECTOR(N-1
DOWNTO 0) Enable, Clock IN STD_LOGIC
Q OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0)
) END COMPONENT
41
Structural description example (4)

• BEGIN
• u1 mux2to1 PORT MAP (w0 gt r(0) ,
• w1 gt
  r(1),
• 
  s gt s(0),
• 
  f gt p(0))
• p(1) lt r(2)
• p(1) lt r(3)
• u2 mux2to1 PORT MAP (w0 gt r(4) ,
• w1 gt
  r(5),
• 
  s gt s(1),
• 
  f gt p(3))
• u3 priority PORT MAP (w gt p,
• y
  gt q,
• z gt ena)
• u4 dec2to4 PORT MAP (w gt q,
• En
  gt ena,

42
Structural description example (5)

• u5 regn GENERIC MAP (N gt 4)
• PORT MAP (D gt z ,
• Enable gt
  En ,
• 
  Clock gt Clk,
• Q
  gt t )
• END structural

43
Sequential Statements
44
Sequential Statements (1)

• If statement
• else and elsif are optional

if boolean expression then statements elsif
boolean expression then statements else
boolean expression then statements end if
45
Sequential Statements (2)

• Case statement
• Choices have to cover all possible values of the
  condition
• Use others to specify all remaining cases

case condition is when choice_1 gt
statements when choice_2 gt
statements when others gt
statements end case
46
Sequential Statements (3)

• Loop Statement
• Repeats a section of VHDL code

for i in range loop statements end loop
47
Sequential Logic Synthesis for Beginners
48
For Beginners

• Use processes with very simple structure only
• to describe
• - registers
• - shift registers
• - counters
• - state machines.
• Use examples discussed in class as a template.
• Create generic entities for registers, shift
  registers, and
• counters, and instantiate the corresponding
  components in
• a higher level circuit using GENERIC MAP PORT
  MAP.
• Supplement sequential components with
• combinational logic described using concurrent
  statements.

49
Sequential Logic Synthesis for Intermediates
50
For Intermmediates

• Use Processes with IF and CASE statements only.
  Do not use LOOPS or VARIABLES.
• Sensitivity list of the PROCESS should include
  only signals that can by themsleves change the
  outputs of the sequential circuit (typically,
  clock and asynchronous set or reset)
• Do not use PROCESSes without sensitivity list
• (they can be synthesizable, but make simulation
  inefficient)

51
For Intermmediates (2)

• Given a single signal, the assignments to this
  signal should
• only be made within a single process block in
  order to avoid
• possible conflicts in assigning values to this
  signal.
• Process 1 PROCESS (a, b)
• BEGIN
• y lt a AND b
• END PROCESS
• Process 2 PROCESS (a, b)
• BEGIN
• y lt a OR b
• END PROCESS

52
Sequential Logic Synthesis for Advanced
53
For Advanced

• Describe the algorithm you are trying to
• implement in pseudocode.
• Translate the pseudocode directly to VHDL
• using processes with IF, CASE, LOOP,
• and VARIABLES.
• Multiple precautions needed,
• Template and examples covered later
• in class.

54
Non-synthesizable VHDL
55
Delays

• Delays are not synthesizable
• Statements, such as
• wait for 5 ns
• a lt b after 10 ns
• will not produce the required delay, and
• should not be used in the code intended
• for synthesis.

56
Initializations

• Declarations of signals (and variables)
• with initialized values, such as
• SIGNAL a STD_LOGIC 0
• cannot be synthesized, and thus should
• be avoided.
• If present, they will be ignored by the
• synthesis tools.
• Use set and reset signals instead.

57
Dual-edge triggered register/counter (1)

• In FPGAs register/counter can change only
• at either rising (default) or falling edge of the
• clock.
• Dual-edge triggered clock is not synthesizable
• correctly, using either of the descriptions
• provided below.

58
Dual-edge triggered register/counter (2)

• PROCESS (clk)
• BEGIN
• IF (clkEVENT AND clk1 ) THEN
• counter lt counter 1
• ELSIF (clkEVENT AND clk0 ) THEN
• counter lt counter 1
• END IF
• END PROCESS

59
Dual-edge triggered register/counter (3)

• PROCESS (clk)
• BEGIN
• IF (clkEVENT) THEN
• counter lt counter 1
• END IF
• END PROCESS
• PROCESS (clk)
• BEGIN
• counter lt counter 1
• END PROCESS

60
Mixing Design Styles Inside of an Architecture
61
VHDL Design Styles
VHDL Design Styles
structural
behavioral
Components and interconnects
Concurrent statements
Sequential statements

• Registers
• Shift registers
• Counters
• State machines

synthesizable
62
Mixed Style Modeling

• architecture ARCHITECTURE_NAME of ENTITY_NAME is
• Here you can declare signals, constants,
  functions, procedures
• Component declarations
• No variable declarations !!
• begin
• Concurrent statements
• Concurrent simple signal assignment
• Conditional signal assignment
• Selected signal assignment
• Generate statement
• Component instantiation statement
• Process statement
• inside process you can use only sequential
  statements
• end ARCHITECTURE_NAME