Register Transfer Level

1
Register Transfer Level And the Arithmetic Logic
Unit
2
Register Transfer Level

• Register Transfer A digital system is
  represented at the register
• transfer level (RTL) when it is specified by the
  following three
• components
• The set of registers in the system
• The operations that are performed on the data
  stored in the registers
• The control that supervises the sequence of
  operations in the system
• Example Register Transfer Operations
• R1 ? R1 R2 Add contents of R2 to R1
• R3 ? R3 1 Increment R3 by 1
• R4 ? shr R4 Shift R4 to the right by 1
• R5 ? 0 Clear R5

3
Algorithmic State Machine
Output Data
External Inputs
Data Processor
Control Logic
Input Data
Status Conditions
Controller Series of instructions to the data
processor Data processor controlled
architecture
4
Register

• A group of flip-flops that stores binary
  information and has the capability of performing
  one or more elementary operations
• Load new information
• Shift the information to the left
• Shift the information to the right
• Counter a register that increments a number
  by one

1
1
1
0
1
1
1
0
5
ALU

• Arithmetic Instruction
• // a b c
• Load R3, b //copy b from memory to R3
• Load R4, c // copy c from memory to R4
• Add R3, R4 // sum placed in R3
• Store R3, a // store the sum to a

Left Operand
Right Operand
R1
R2
R3
ALU

Rn
Result
6
ALU

• Logic Instruction
• // a b c
• Load R3, b //copy b from memory to R3
• Load R4, c // copy c from memory to R4
• XOR R3, R4 // XOR placed in R3
• Store R3, a // store the result to a

Left Operand
Right Operand
R1
R2
R3
ALU

Rn
Result
7
Arithmetic Logic Unit
Operand A Operand B Logic/Arithmetic Function
Select
ALU
Output
8
Arithmetic Logic Unit/Function Generator
F3 F2 F1 F0
Operand A Toggles 0-3 Operand B Toggles
4-7 Logic/Arithmetic
A3 A2 A1 A0
ALU SN74181
Output Lamps 4-7
B3 B2 B1 B0
S3 S2 S1 S0
Function Select Lamps 0-3
Clk
SN74163
9
Algorithmic State Machine
Output Data
External Inputs
Data Processor
Control Logic
Input Data
Status Conditions

• All binary information is one of the following
• Data
• Control info

10
Algorithmic State Machine
Name
Binary Code
Register Operation or Output
General Description
11
Algorithmic State Machine
Name
Binary Code
Register Operation or Output
General Description
T3
011
R?0 START
Example
12
Algorithmic State Machine
0
1
Condition
Exit Path
Exit Path
Decision Box
13
Algorithmic State Machine
Register Operation or Output
Conditional Box
14
Algorithmic State Machine
T1
001
Start
0
1
E
R?0
T2
010
F?E
15
Algorithmic State Machine
001
EF 00
E 1
EF 01
100
010
011
16
Algorithmic State Machine
T1
001
Start
0
1
E
R?0
0
1
F
T2
100
T2
010
T2
011
F?E
F?E
F?E
17
Algorithmic State Machine
Design Example Binary Multiplier 23 10111 mul
tiplicand 19 10011 multiplier
Z1 if P0
Z
Control Logic
Check for zero
Q0
Multiplicand
Register B
P Counter
S
Cout
Parallel Adder
n
Sum
Multiplier
Register A
C
0
Register Q
18
ASM Chart for Binary Multiplier
T0
Initial State
0
S
T1
1
A?0 C?0 P?n
T2
P?P-1
0
1
Q0
A?AB, C?Cout
T3
Shift Right CAQ, C?0
0
1
Z
19
Control Logic
Two-Stage Design Process 1. Design the
register transfers in the datapath 2. Design
the Control Logic Rectangular Blocks (State
Boxes) States of a Sequential Circuit Diamond
Shaped Blocks (Decision Boxes) Conditions for
the transition to the next state
20
Control Logic
Rectangular Blocks (State Boxes) States of a
Sequential Circuit Diamond Shaped Blocks
(Decision Boxes) Conditions for the
transition to the next state T0
Initial State T1 A ? 0, C ? 0, P ? n,
T2 P ? P-1 if Q0 1 then A ? A B, C ?
Cout T3 shift right CAQ, C ? 0
S0
Z1
T1
T0
T2
T3
S1
Z0
21
Control Logic
S0
Z1
T1
T0
T2
T3
S1
Z0
T0
Z S
Control Logic
T1
T2
T3
L Q0T2
Q0
L is a signal that indicates loading the sum into
register A
22
Control Logic
S0
Z1
T1
T0
T2
T3
S1
Z0
STATE BINARY ONE-HOT T0 00
0001 T1 01 0010
T2 10 0100 T3
11 1000