CSE430 Term Project Overview

1
CSE430 Term Project Overview

• Yuyan Xue
• Department of Computer Science and Engineering
• University of Nebraska-Lincoln
• 09/05/2008

2
Introduction

• Goal
• Reinforce your understanding on pipelining RISC
  processor learnt from the class
• Learn to design and implement a pipelining
  process for supporting embedded system
  applications
• Practice teamwork

3
Group Formation

• Team-based work (3-4 Team members)
• Task assignment
• System design and implementation
• Sketch design
• Component design and function validation
• Pipelining design and function validation
• Assembler design (c, java, perl, .)
• Application program design (assembly language)
• Team leader (meeting, documentation)
• Website maintainer

4
Project Facilities

• Altera UP2 education board and manual
• Altera Quartus II Web Edition software
  (downloadable from website)
• ByteBlasterMV parallel port download cable

5
Design Flowchart
Quartus II
Component Design and Validation
Processor Sketch Design
Pipelining Design and Validation
(.mif file)
Compiling and Download
Assembler Design
Application Program Design
On-board Debugging
6
Processor Sketch Design

• Instruction and data bus width
• Register file sizes
• Instruction memory size
• data memory size
• Instruction format and instruction set
  (application dependent)

7
Processor Component Design

• Quartus II logic Design
• Schematic or VHDL/Verilog
• Basic Components
• Decoder, Register files, ALU and Pipeline
  registers
• Ready to use components IM (LPM_ROM) and
  DM(LPM_RAM)
• Supplementary Components
• clock
• Forwarding units
• I/O

8
Design Validation

• Quartus II Simulation
• Vector Waveform File
• Layered Validation
• Component Level
• Processor Level
• Pipelining Level

9
Application Program Design

• Use MIPS assembly language
• Choose one of the applications
• Vending machine controller
• Matrix multiplication
• Obey the instruction set design
• Obey the processor structure design
• Register files numbers
• IM and DM size
• Handle possible hazards and stalls
• Forwarding unit
• Branch prediction

10
Assembler Design

• Choose any high-level development language
• Java, C, C, Perl
• Design Steps
• Resolve all symbol
• Convert application program to machine code
  (according to your instruction set design)
• Follow Memory Initialization Format (MIF) that
  Altera specifies

11
Download and Debugging

• Device Assignment
• FLEX10KEPF10K70RC240-4
• Pin Assignment
• Design Download
• w logical design fully tested
• w mif file ready
• ByteBlaster cable to UP2
• On Board Debugging

12
Important Milestones

• Group formation (Sep. 8)
• Sketch Design (Oct. 6)
• Pipelining Design and Validation (Oct. 27)
• Application program and assembler (Nov. 17)
• Project Demo (Dec. 8-12)

13
Useful Links

• Project Specifications and Description
• Quartus II license and installation 
• Altera Quartus II license webpage
• Altera Quartus II installation instructions
• Introduction to Quartus II
• compact version
• longer version
• ByteBlaster II download cable user Guide