Computer Organization - PowerPoint PPT Presentation

1 / 57
About This Presentation
Title:

Computer Organization

Description:

... memory (CD-ROM) is originally developed by Phillips and Sony for recording music. ... FireWire is a high-speed serial interface that transfers data in packets, ... – PowerPoint PPT presentation

Number of Views:41
Avg rating:3.0/5.0
Slides: 58
Provided by: silver3
Category:

less

Transcript and Presenter's Notes

Title: Computer Organization


1
Lecture 4
  • Computer Organization

2
Computer Hardware
CPU
Memory
Input/Output
3
Computer Hardware
  • Arithmetic Logic Unit (ALU) performs arithmetic
    and logic operations.
  • Register are fast stand-alone storage locations
    that hold data temporarily.
  • Data register, instruction register, program
    counter.
  • Control Unit controls the operation of each part
    of the body.

4
Main Memory
  • Main memory is a collection of storage location,
    each with a unique identifier called the address.

Addresses
Values
000000000 000000001 000000010 ... 111111110 111111
111
01100110 01011011 01100101 ... 101010110 101001000
5
Main Memory
  • Data are transferred to and from memory in groups
    of bits called words. A word can be a group of 8
    bits, 16 bits, 32 bits or sometimes 64 bits.
  • 8-bit word is referred to a byte, 16-bit word is
    referred to a 2-byte word, and so on.
  • To access a word in memory requires an
    identifier, The total number of uniquely
    identifiers identified the address space.

6
Address Space
Unit Exact Number of Bytes
Approximation Kilobyte 210 (1,024)bytes
103 bytes Megabyte 220
(1,048,576)bytes 106 bytes Gigabyte
230 bytes 119
bytes Terabyte 240 bytes
1112 bytes Petabyte 250 bytes
1115 bytes Exabyte 260
bytes 1118 bytes
7
Memory Address
  • Because computers operate by storing numbers as
    bit pattern, the address itself is also
    represented as a bit pattern.
  • If a computer has 64 kilobytes (216) of memory
    with a word size of 1 byte, then to define the
    address, you need a bit pattern of 16 bits.
  • The first location is referred to as address
    0000000000000000 (address 0), and the last
    location is referred to as address
    1111111111111111 (address 65535).

8
Memory Address
  • A computer has 32 MB (megabytes) of memory. How
    many bits are needed to address any single byte
    in memory?
  • The memory address space is 32 MB, or 225 byte.
    This means you need 25 bits, to address each
    byte.

9
Memory Address
  • A computer has 128 MB of memory. Each word in
    this computer is 8 bytes. How many bits are
    needed to address any single byte in memory?
  • The memory address space is 128 MB, which means
    227 byte. However each word is 8 (23) bytes,
    which means you have 224 words. This means you
    need 24 bits to address each word.

10
Memory Type
  • Random access memory (RAM) makes up most the main
    memory in a computer. The user can write
    something to RAM and later erase it by
    overwriting it. It is volatile the information
    is erased if the system is powered down.
  • Read-only memory (ROM) are written by the
    manufacturer the user is allowed to read but not
    write to ROM. Its advantage is that it is
    nonvolatile its contents are not erased if you
    turn off the computer.

11
Memory Hierarchy
Fastest Speed (Registers) Faster Speed (Cache
Memory) Fast Speed (Main Memory)
  • Use a very small amount of high-speed memory
    where speed is crucial
  • Use a moderate amount of medium-speed memory to
    store data that are accessed often.
  • Use a large amount of low-speed memory for data
    that are not accessed very often.

12
Cache Memory
  • Cache memory, which is normally small in size, is
    placed between the CPU and main memory.

CPU
Memory
Cache
13
Cache Memory
  • Cache memory at any time contains a copy of
    portion of main memory. When the CPU needs to
    access a word in main memory, if follows this
    procedure
  • The CPU checks the cache.
  • If the word is there, it copies the word if not,
    the CPU accesses main memory and copies a block
    of memory starting with the desired word.
  • The CPU accesses the cache and copies the word.

14
Input/Output
  • This subsystem allows a computer to communicate
    with the outside world and to store programs and
    data even when the power is off.
  • Input/Output devices can be divided into two
    broad categories
  • Non-storage devices.
  • Storage devices.

15
Non-storage Device
  • Non-storage device allow the CPU/memory to
    communicate with the outside world.
  • The keyboard provides input the monitor displays
    output and at the same time echoes the input
    typed on the keyboard.

16
Storage Device
  • Storage device are cheaper than main memory, and
    their contents are nonvolatile.
  • They are sometimes referred to as auxiliary
    storage devices.
  • We categorize them as either magnetic or optical.

17
Magnetic Storage Device
  • Magnetic storage device use magnetization to
    store bits of data. If a spot is magnetized, it
    represents 1 else it represents 0.
  • A magnetic disk is one or more disks stacked on
    top of each other. The disks are coated with a
    thin magnetic film. Information is stored on and
    retrieved from the surface of the disk using a
    read/write head for each magnetized surface of
    the disk.

18
Magnetic Storage Device
  • Physical layout of a magnetic disk.

19
Magnetic Disk
  • Surface organization of a disk.

20
Magnetic Disk
  • To organize data stored on the disk, each surface
    is divided into tracks, and each tracks divided
    into sectors.
  • The tracks are separately by an inter-track gap,
    and the sectors are separately by an inter-sector
    gap.

21
Magnetic Disk
  • A magnetic disk is considered a random access
    device. However, the smallest storage area that
    can be access at one time is a sector.
  • The performance of a disk depends on several
    factors.
  • The rotational speed.
  • The seek time.
  • The transfer time.

22
Magnetic Tape
  • One common type of magnetic is mounted on two
    reels and uses a read/write head that reads or
    writes information when the tap is passed through
    it.

23
Magnetic Tape
  • The width of the tap is divided into nine tracks
    each spot of a track can store 1 bit of
    information. Nine vertical spots can store 8 bits
    of information related to a byte plus a bit for
    error detection.

24
Magnetic Tape
  • Although the surface may be divided into blocks,
    there is no addressing mechanism to access each
    block.
  • To retrieve a specific block on the tape, need to
    pass through all of the previous blocks.
  • Magnetic tap is cheaper than magnetic disk, but
    its slower.

25
Optical Storage Devices
  • Optical storage devices use laser to store and
    retrieve data.
  • Devices that use the technology include CD-ROMs,
    CD-Rs and CD-RWs.
  • The compact disk read-only memory (CD-ROM) is
    originally developed by Phillips and Sony for
    recording music.

26
Optical Storage Devices
  • The steps in creating and using a CD-ROM.

27
Optical Storage Devices
  • The compact disk recordable (CD-R) allows user to
    create one or more disks without going through
    the expense involved in creating CD-ROMs.
  • The user can write once to the disc, but it can
    be read many time. This is why it is sometimes
    called write once, read many (WORM). CD-R
    technology uses the same principles as CD-ROM to
    create a disc.

28
Optical Storage Devices
  • To overwrite previous materials, there is a new
    technology that creates a new type of disc called
    compact disc rewritable (CD-RW). CD-RW technology
    uses the same principle as CD-R to create a disc.

29
Subsystem Interconnection
  • The CPU and memory are normally connected by
    three groups of wires, each called a bus
  • Data bus, address bus and control bus.

CPU
Memory
Data Bus
Address Bus
Control Bus
30
Subsystem Interconnection
  • The data bus is made of several wires, each
    carrying 1 bit at a time. The number of the wires
    depends on the size of the word.
  • The address bus allows access to a particular
    word in memory. The number of wires in the
    address bus depends on the address space of
    memory.
  • If the memory has 2n word, the address bus needs
    to carry n bits at a time.

31
Subsystem Interconnection
  • Control bus carries communication between the CPU
    and memory. The number of wires used in the
    control bus depends on the total of control
    commands a computer needs.
  • If a computer has 2m control actions, it need m
    wires for the control bus because m bits can
    define 2m different operations.

32
Connecting I/O Devices
  • The I/O devices cannot be connected directly to
    the buses that connect the CPU and memory.
  • The I/O devices are electromechanical, magnetic,
    or optical devices, whereas the CPU and memory
    are electronic devices.
  • The I/O devices are attached to the buses through
    what is called an I/O controller or interface.

33
Connecting I/O Devices
  • There is one specific controller for each I/O
    device.

34
Connecting I/O Devices
  • A controller can be a serial or parallel device.
  • A serial controller has only one wire connection
    to the device.
  • A parallel controller has several connections to
    the device so that several bits can be
    transferred at a time.

35
Connecting I/O Devices
  • The small computer system interface (SCSI) has a
    parallel interface with 8, 16, 32 wires. The SCSI
    interface provides a display chained connection.

36
Connecting I/O Devices
  • FireWire is a high-speed serial interface that
    transfers data in packets, achieving a transfer
    rate of up to 50 MB/sec.

37
Connecting I/O Devices
  • The universal serial bus (USB) is also a serial
    controller used to connect devices such as the
    keyboard, mouse and so on to a computer.

38
Connecting I/O Devices
  • The CPU usually uses the same bus to read data
    from or write data to main memory and the I/O
    device.
  • If the instruction refers to a word in memory,
    data transfer is between main memory and the CPU.
  • If the instruction identifies an I/O devices,
    data transfer is between I/O device and the CPU.

39
Connecting I/O Devices
  • In the isolated I/O method, the instructions used
    to read/write memory are totally different from
    the instructions used to read/write I/O devices
  • Each I/O has its own address. The I/O address can
    overlap with memory addresses without and
    ambiguity because the instruction itself is
    different.

40
Connecting I/O Devices
  • For example, the CPU can use the command Read 05
    to read from memory word 05, and it can use the
    command input 05 to read from I/O device 05.

41
Connecting I/O Devices
  • In the Memory-Mapped I/O method, the CPU treats
    each register in the I/O controller as a word in
    memory.
  • The CPU does not have separate instructions for
    transferring data from memory or I/O devices.
  • There is only one Read instruction to read data
    from memory or I/O device.

42
Connecting I/O Devices
  • If the address defines a register from an I/O
    device, the data are read from that register. If
    the address defines a word from memory, the data
    are read from that word.

43
Connecting I/O Devices
  • The advantage of the memory-mapped configuration
    is a smaller number of instructions all the
    memory instructions can be used by the I/O
    devices.
  • The disadvantage is that the part of address
    space used for memory is allocated to the
    registers in the I/O controllers.

44
Program Execution
  • The CPU uses repeating machine cycles to execute
    instructions in the program, one by one, from
    beginning to end.
  • A simplified cycle can consist of three steps
  • Fetch, decode and execute.

No
Fetch
Decode
Execute
More Instructions ?
Yes
Start
Stop
45
Program Execution
  • In the fetch step, the control unit orders the
    system to copy the next instruction into the
    instruction register in the CPU.
  • When the instruction is in the instruction
    register, it gets decoded by the control unit.
  • After the instruction is decoded, the control
    unit sends the task order to a component in the
    CPU to execute.

46
Program Execution
  • A computer with simple architecture needs at
    least four instructions for adding two integers.
    The four instructions and two input integers
    reside in memory before program execution the
    result will be in memory after program execution.
  • Assume that the numbers and address are decimal,
    the instructions are in memory address 70, 71, 72
    and 73 and input data are stored in locations 200
    and 201.

47
Program Execution
  • The memory and CPU before execution of the
    program.

48
Program Execution
  • The results of first and second operations on the
    memory and address.

49
Program Execution
  • The results of first and second operations on the
    memory and address.

50
Input/Output Operation
  • There is a need for commands to transfer data
    from the I/O devices to the CPU and memory.
  • Because I/O devices operate at much slower speeds
    than CPU, the operation of the CPU mush be
    somehow synchronization
  • Programmed I/O, interrupt-driven I/O and direct
    memory access (DMA).

51
Input/Output Operation
  • In the programmed I/O method, synchronization is
    very primitive the CPU wait for the I/O device.
  • The big issue is that CPU devices is wasted by
    checking the status of the I/O device for data to
    be transferred.

52
Input/Output Operation
  • In the interrupt-Driven I/O method, the I/O
    device informs (interrupts) the CPU when it is
    ready.
  • During this time, the CPU can do other jobs.

53
Input/Output Operation
  • Direct Memory Access (DMA) transfers a large
    block of data between a high-speed I/O devices,
    such as a disk and memory directly.
  • This requires a DMA controller that relieves the
    CPU of some of its functions. The DMA controller
    has registers to hold a block of data before and
    after memory transfer.

54
Input/Output Operation
  • The DMA connection to the general bus.

55
Input/Output Operation
  • In this method, for an I/O operation, the CPU
    sends a message to the DMA.
  • The message contains the type of transfer, the
    beginning address of the memory location, and the
    number of bytes to be transferred.
  • The CPU is now available for other job.

56
Input/Output Operation
  • When ready to transfer data, the DMA controller
    informs the CPU that it needs to take control of
    the buses.
  • The CPU stops using the buses and lets the
    controller use them.
  • After data transfer, directly between the DMA and
    memory, the CPU continues its normal operation.

57
Input/Output Operation
  • The CPU is idle during the data transfer between
    the data transfer between DMA and memory.
Write a Comment
User Comments (0)
About PowerShow.com