Ceg3430

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Ceg3430

• High Speed Logic CircuitsRevision exercises

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Chapter 1a Fundamentals

• Define the term Knee-frequency.
• The Knee-frequency of a circuit is at 250MHz,
  what information does it give to a digital system
  designer? Does it give any information about the
  long-term response of the circuit?
• Study Fig 1.6 of Page 13 of ref.1, the
  equivalent resistance as seen by the capacitor
  being tested is 503 Ohms as shown in Fig. 1.8. Do
  you agree with this result, and what is your
  calculation?
• Study Fig. 1.16 of Ref.1 and explain why
  unused inputs should be connected to ground or
  Vcc.
• What special features a DSO should have if it is
  used to measure capacitance by the following
  methods (a) Step response method (b) total area
  under a response curve method.

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Chapter 1b Fundamentals

• Explain why the total response method has a more
  accurate result.
• List methods to reduce cross talk among
  components on a PCB.
• A clock pulse with rise time (Tr)5ns is
  transmitting in a FR4 PCB outer trace. Specify
  the maximum length of the trace if it is a lumped
  circuit. What will happen to the signal if trace
  is longer that that length?
• Why is it important to measure inductance of the
  traces of a PCB, especially the traces that carry
  Vcc and ground?

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Chapter 2 High speed properties

• Check Input capacitance Ci and input current Ii
  of a Xilinx XC95108.
• For active power dissipation of a logic device on
  capacitive loads, why the energy does not depend
  on the resistors of the drive circuit?
• For the shared bus example in Fig.2.8, calculate
  power for Fclock8MHz
• For fig.2.14, show max(dIcapacitor/dt)1.52??V?C/T
  r2 . How true is it? Do you believe it? If not,
  give your formulation.
• Work out the noise margin for a TTL-74-240 gate.
• Why do we dislike large dI/dt? And how to reduce
  dI/dt for a circuit.
• For high pull up resistors as shown in fig.2.22,
  we add capacitors to reduce cross talk. Show
  Cross-talkCM/C1.

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Additional exercises

• Ceg3480

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Q1 Maximum allowable rise time

• The voltage specification of a digital device is
  
• V input high from 2 V to 5.5V
• V input low from 0 V to 0.8 V
• V output high from 2.5V to 5.5V
• V output low from 0 to 0.35V
• (a) Calculate the high noise margin, low noise
  margin and overall noise margin.
• (b) The output of this device is connected to a
  capacitive load of 50pF, the ground pin
  inductance is 15nH, what is the minimum allowable
  T10-90 rise time for the output? Given that the
  maximum current change of a capacitor C is (1.52
  ? maximum voltage ? C)/ (T10-90)2.

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Answers of Q1

• a) 0.45V
• b) 3.9ns

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Q2 Time delay

• A digital output pin is connected in parallel to
  10 inputs of CMOS gates (15pF input capacitance
  for each input). The total trace that connects
  the output and the inputs has a capacitance of
  3pF/in, and the length of the trace is 10 in. Vcc
  of the system is 5V.
• Calculate the total capacitance at the digital
  output pin.
• If the total resistance from the output pin to
  ground is 80?, calculate the minimum time delay
  of the signal from the output pin to the inputs
  of CMOS gates.
• Estimate the maximum frequency of the signal that
  can be used in the system, and state the
  justifications for your estimation.
• Calculate the maximum active power consumption
  for this system if the digital signal has a
  frequency of 10 MHz.

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Answers of Q2

• A) 180p
• B) 31.68ns
• C) Around 11.9MHz (with 20ns margin)
• D) 0.02W

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Q3 high speed properties

• In a digital circuit interface, the output of a
  CMOS gate A is driving 15 inputs of similar gates
  (Cin20pF each) through a long trace (2pF/in.) of
  20 inches. (All capacitive loads are assumed to
  be in parallel). The high side drive resistance
  of A is Rh (120?). A square wave of Fclock is
  connected to the input of A. The power supply is
  5 Volts.
• State any assumptions you used in the following
  calculations.
• Draw the equivalent circuit.
• Calculate the total capacitance Ct observed by
  the output of A.
• Prove that the time delay caused by this
  interface is approximately 2.2 Rh Ct.
• What is the maximum clock frequency Fclock this
  circuit can tolerate?
• Estimate the power dissipation of this system
  when Fclock is 5MHz.

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Answers of Q3

• A)
• B)340pF
• C)
• D) approximately 5.26MHZ
• E) 0.0425W

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Q4 cross talk

• In the following circuit, the noise margin of the
  buffers is 0.4Volts and the Vcc of the system is
  5 Volts. The output impedance of the buffers is
  Ro(100 ?) and the input impedance is Ri (10M?).
  We take the assumption that the only mutual
  capacitance exists in the circuit is Cm, and the
  rise time of the input pulse is Tr.
• If switch S is at position A (open circuit),
  derive the cross talk relation between E and D.
• If switch S is at position A (open circuit),
  calculate the shortest allowable rise time (Tr)
  of the input pulse Vin that would not cause any
  noise at Output2.
• If switch S is at position B (connected to an
  output), calculate the shortest allowable rise
  time (Tr) of the input pulse Vin that would not
  cause any noise at Output2.
• If switch S is at position C (connected to a
  capacitor) and the rise time of the input pulse
  (Tr) is 1ns, calculate the minimum value of X
  that the input pulse would not cause any noise at
  Output2.
• Discuss how to reduce cross talk in a
  circuit.Input pulse (Vin)

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Q5 high speed logic circuit

• In a digital circuit interface, the output of a
  CMOS gate A is driving two groups (group1 and
  group2) of inputs.
• Group 1 has 12 gates each input has a capacitance
  of 10pF.
• Group 2 has 6 gates each input has a capacitance
  of 15pF.
• The high side drive resistance of all gates is Rh
  (100?). A square wave of Fclock is connected to
  the input of A. The power supply voltage (Vcc) is
  5 Volts.
• State any assumptions you used in the solving the
  following questions.
• Draw the equivalent circuit.
• Calculate the total capacitance Ct observed by
  the output of A.
• If the rise time of an output is defined as the
  duration between the output at 15 and the
  output at 85 of the maximum output voltage.
  Calculate the time delay caused by this interface
  circuit.
• Estimate the maximum clock frequency Fclock this
  circuit can tolerate?
• Estimate the power dissipation of this system
  when Fclock is 5MHz.

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Answer to Q5

• (2) Ct210pF
• (3) 36.5ns
• Estimate the maximum clock frequency Fclock this
  circuit can tolerate?
• (4) 12.8MHz
• (5) 0.02625Watts

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Q6

• A digital output pin is connected in parallel to
  20 inputs of CMOS gates (10pF input capacitance
  for each input) . The trace that connects the
  output and the inputs has capacitance of 3pF/in,
  and the length of the trace is 8 in.
• Calculate the total capacitance at the digital
  output pin.
• If the total resistance from the output pin to
  ground is 150? when it is switching from low to
  high, calculate the minimum time delay of the
  signal from the output pin to the inputs of CMOS
  gates.
• Estimate the maximum frequency of the signal that
  can be used in the system, and state the
  justifications for your estimation.
• Calculate the maximum power consumption for this
  system if the digital signal has a frequency of 5
  MHz.

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Answer to Q6

• 1)224pF.
• 2) 74 ns
• 3) 5.95MHz.
• 4) 0.028 W.

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Q7

• The gate below has a noise margin of 0.25V, the
  capacitive load is 20pF and LGND is 40nH.
• Estimate the shortest rising edge of the input
  that can be applied to the system.
• Calculate the power consumption of the circuit is
  the input is at 10MHz.

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Answer to Q7

• 1)Trgt4.93ns
• 2) 5mW

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Q8

• The circuit shows gates A and B are placed closed
  to each other, however, the cross talk is
  required to be below 5.
• A)If C1 is 0.005?F, what is the shortest
  allowable rise time of the signal at Ain.
• B) If C1 is removed, what is the shortest
  allowable rise time of the signal at Ain.

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Answer to Q8

• ANS
• A) ( Cm/C1)lt5/100,
• B)Trgt0.8us