Ceg3430 Chapter 2 Robot 2

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Ceg3430Chapter 2 Robot 2

• Micro-controller or
• embedded controller

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Content

• 1. Introduce the family
• 2. General description of the 8031 processor
• 3. Memory Interface
• 4. Parallel port interface
• 5. Serial Interface
• 6. Interrupt

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References

• Intels database
• http//developer.intel.com/design/mcs51/
• Philips database
• http//www-us2.semiconductors.philips.com/products
  /
• Paulmon, a freeware
• www.ece.orst.edu/paul/8051-goodies/goodies-index.
  htmlpaulmon
• On Basic52 by Jan Axelson
• http//www.lvr.com/microc.htm
• Flash ROM based 89C51
• http//www.atmel.com/atmel/products/prod71.htm

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A simple micro-controller (e.g. 8048) has

• CPU (Central Processing Unit)
• Some internal Ram (1K-byte) and a few (48)
  kilobytes of ROM for holding programs.
• Parallel input/output bus so that it can
  communicate with the outside world.
• Be able to take hardware interrupt.

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Additional feature of a micro-controller (8031)

• Serial input/output so that it can make more
  distant communications with other computers.
• Timers for counting or generating exact timing
  signals for control purposes.
• Power down circuit to keep the internal data even
  the main power is cut off.

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1.Introduce the Intel 8051 family8032/8051/8052

• http//developer.intel.com/design/mcs51/
• Features
• on chip RAM
• (8x31gt128 bytes 8x51gt256 bytes),
• on chip ROM or simple memory interface
• on chip timer(8xx1gt2 timers, 8xx2gt3 timers),
• on chip interrupt support
• Serial (UART), parallel port interface
• new products support up to 33MHz clock rate.

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8031 family

• All have 128 bytes RAM, 2 timers, 32-bit parallel
  IO, serial IO, 5 interrupt sources
• 8031 ROM-less use external ROM for program
• 8051 4K-byte ROM
• 8751 4K-byte UV-EPROM (ultra-violet erasable,
  re-programmable)
• 8951 8K-byte (Electrical erasable,
  re-programmable)

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8031 family

• All have 128 bytes RAM, 2 timers, 32-bit parallel
  IO, serial IO, 5 interrupt sources
• 8031 ROM-less 8051 4K-byte ROM
• 8751 4K-byte UV-EPROM (ultra-violet erasable,
  re-programmable)
• 8951 8K-byte (Electrical erasable,
  reprogrammable)
• Philips extended Architecture (16-bit with AD
  converter)

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Philips 80C51 16-bit extended architecture (XA)
for industrial control

• http//www-us2.semiconductors.philips.com/products
  /
• The XA-C3,
• supports the full Controller Area Network (CAN)
  2.0B. It supports both 11-bit and 29-bit
  identifiers (ID) at up to 1Mbit/s data rate. It
• The XA-S3,
• 8-channel 8-bit ADC (4.6ms conversion)
• 16 M-byte (24 bit) addressing
• I²C-bus serial I/O port

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2. General description of 8051

• 8/16/32 Kbyte On-Chip ROM/EPROM program memory
• 256 x 8-bit RAM
• 32 Programmable I/O Lines
• Three16-Bit Timer/Counters
• 7 Interrupt Sources
• Quick-Pulse EPROM Programming (8751 contains
  4Kbyte UV-EPROM)
• Programmable Serial Port
• 32k32K External Program Memory Space
• 32K32k External Data Memory Space
• IDLE and POWER DOWN Modes

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8XC51FX pin assignment
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Memory Addressing for the 8051 family

• Memory space
• 128 bytes internal RAM space
• address 0-7F (hex) internal data ram,
• 80-FF internal data and special function
  registers SFR overlapped addressed by indirect
  and direct mode resp.
• 64K program space includes
• The lower 4K( or more depends on specific device)
  on chip ROM/EPROM (if exist)
• The rest is external memory
• 64K external data memory
• External interface uses pins /ALE,/PSEN,
  IO_PORTS.

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FFFF
32k
SFR Special Function Register
0FFF
SFR
32k
http//developer.intel.com/design/mcs51/manuals/27
2383.htm
Program Latch Enable
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Special Function Registers at internal RAM
address 80 -- FF hex
Accumulator
Interrupt priority
Stack pointer
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Important Pins

• Reset
• ALE Address Latch Enable, to latch address
  outputs at Port0 and Port2
• PSEN Program Store Enable
• Port 0
• port 1
• port 2

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Power up and after

• First let us look at what the 8031 system will do
  after reset.
• Power-up or reset. first instruction from 0000H
• A simple startup assembly segment is as follows
• 1 Org 0 after reset
• 2 ljmp start long jump to start at line
• 3 Org 30h arbitrary, but addr.
• 4 start mov sp,30h-1 set stack point at 30h
• Question Guess why sp 30h-1 not 30h?

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External program ROM interface
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Address Latch Enable
Program Store Enable
A0-A15 16 bit 64K-byte address
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To connect more memory

• Use 138 and A12 to do address decoding

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3. Parallel interface 8255

• Treated as memory location at E000H
• Read/write registers as memory data access

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4. Serial Interface

• SM0 SM1 Mode serial Baud rate
• 0 0 0 F.osc./12 (8-bit)
• 0 1 1 depends on Timer 1
• 1 0 2 F.osc./64 or F.osc./32
• 1 1 3 Depends on Timer 1

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5. five sources of interrupt

• TF0 Timer0, Start address 0003H
• TF1 Timer1 Start address 000BH
• INT0 External0 (from external pin /INT0) Start
  address 0013H
• INT1 External1 (from external pin /INT1) Start
  address 001BH
• Serial IO interrupt Start address 0023H