Introduction to Digital Design 55:032

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Introduction to Digital Design55032

• Final Exam Review

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General Information

• 2 hour exam - open book, open notes
• Eight problems
• 2 over 1st third
• 3 over 2nd third
• 3 over material since last exam
• Go over the reviews for the first and second
  exams (combinational and sequential logic)

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Chapter 7 Registers and Reg. Transfers

• Registers
• Registers are groups of flip-flops with some
  common characteristics
• common clock and/or controls
• common data function (counters, storage reg.)
• There are two ways to control when a register
  changes state
• Synchronous enable controls the FF inputs
• Clock gating enable is ANDed with clock

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Chapter 7 (cont.)

• Register transfers and RTL
• More formalized method of describing information
  processing and flow in a system
• General form is
• condition destination ? source expression
• Source expression operations classified as
  transfer, arithmetic, logical, and shift
• A transfer is expected to complete at the next
  clock transition where the condition is true

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Chapter 7 (cont.)

• Register Transfers and RTL
• Elementary register transfer operation are
  microoperations
• Define data sources and function
• Define transfer destination
• Generally assumed to complete in one clock cycle

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Chapter 7 (cont.)

• Micro-operations are combinational logic
  functions
• Transfer, Arithmetic, Logical, Shift
• Many datapaths have a multifunction ALSU to
  perform these operations
• Some datapaths have only enough logic to perform
  a specific set of u-ops

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Chapter 7 (cont.)

• Data Transfer
• Registers may have multiple data sources we must
  select
• Multiplexers
• Dedicated or shared
• Data busses
• Memory transfers need both address and data
  information
• Both source (READ) and destination (WRITE)

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Chapter 7 (cont.)

• Data Transfer may be parallel or serial
• Parallel all data bits moved from register to
  register at the same time (one clock period)
• Faster
• more wiring needed
• Serial data bits move from source register to
  destination register one bit at a time (n clocks)
• need P. to S. and S. to P. shift registers
• only one signal needed

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Chapter 7 (cont.)

• Bidirectional Data Transfer
• Single signal used to send and receive data
• Solves distributed multiplexing problem
• Cuts total number of data lines in half
• Three-State Output Buffers
• Needed to implement bidirectional signals
• Three states are high (1), low (0) and off (hi-z)
• Output Enable signal controls output on or off

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Chapter 7 (cont.)

• Counter is a sequential circuit that cycles
  through a defined set of states
• Synchronous
• Ripple
• Many different variations
• binary, decimal, other sequence
• up, down, or both
• parallel load, clear, enable, ripple carry out
• A counter with no inputs is an Autonomous
  sequential circuit

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Chapter 7 (cont.)

• Arbitrary count sequences
• Classic sequential circuit design
• Define state diagram go from there
• Must ensure unused states have path to normal
  count sequence
• Controlled standard counter
• Detect max value clear counter
• Use carry out signal to load initial count value

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Chapter 7 (cont.)

• Ring and twisted ring counters
• Both use shift register as basic element
• Ring feeds back SR true output to input
• For n FFs there are n states
• Must initialize counter to 00001
• Must handle unused states
• Twisted ring feeds back SR false output to input
• For n FFs there are 2n states
• Counter can be initialized to all zeros (cleared)

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Chapter 8 - Sequencing and Control

• The Control Unit (CU) ensures that the correct
  sequence of micro-operations is performed by the
  DataPath Unit (DPU)
• The sequence of CU states corresponds to the
  sequence of DPU control words.
• The DPU status bits are tested by the CU to
  determine the CU next state transitions.
• CUs are just sequential circuits just more
  complex especially for computer CUs

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Chapter 8 (cont.)

• Algorithmic State Machine (ASM) charts are
  another way to document CU operation
• Each state is defined by an ASM block
• Each ASM block is defined by the following ASM
  elements
• State Box (mandatory) - captures state name and
  any Moore-type outputs and the optional state
  code
• Decision Box - tests inputs to determine next
  states and possible conditional outputs
• Conditional Output Box - defines any conditional
  Mealy outputs

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Chapter 8 (cont.)

• Hardwired CUs are generally faster than
  micro-programmed CUs but less flexible and harder
  to design and modify
• Primarily used when CU is relatively simple and
  task is fixed
• Hardwired CU types are
• Classical Sequential Circuits
• One FF per state (One Hot)
• Sequence register and decoder

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Chapter 8 (cont.)

• Micro-programmed CUs
• DPU control words stored in PROM
• The sequencer determines the control store
  address and therefore the sequence of
  micro-operation to be performed
• Sequencer consists of Control Address Register
  (CAR) and next address logic
• Part of each control store location is used to
  determine the next CAR value

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Chapter 8 (cont.)
Microprogrammed CU Block Diagram
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Chapter 8 (cont.)

• Absolute next CAR values are effectively the same
  as next state values
• Next CAR controls can also be relative i.e. NEXT
  (CAR ? CAR 1)
• Certain techniques also do multi-way branches
  (needed for next CAR value determined by
  instruction opcode)
• Micro-programmed CALL and RETURN can also be
  implemented.

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Chapter 8 (cont.)

• Instruction Mapping - a method for doing
  opcode-based multi-way branches
• Assumes instructions sequences are defined and
  the starting location known for each
• A PROM is the programmed with each inst. sequence
  starting address at the PROM location which
  instruction opcode value
• After FETCH and opcode is read, the opcode
  selects the correct first micro-instruction from
  the Mapping Lookup table and loads the CAR with it

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Chapter 9 - Memory Basics

• Memory
• Signal types
• Address, Data, Control
• Size and configuration
• Total bits vs. locations x bits/loc.
• RAM (read/write) and ROM (read only)
• Typical read and write operations
• Static and dynamic memory

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Chapter 9 (cont.)

• Memory Arrays
• Must determine total number of ICs needed and
  organization of array
• For desired memory of i locs of x bits/loc
• Using memory ICs of j locs of y bits/loc
• No. array rows Nr i/j (round up to next
  integer)
• No. array cols. Nc x/y (round up to next
  int.)
• Total ICs Nr Nc
• Decoder selects rows from upper address lines

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Generalized Memory Array
Decoder
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Chapter 10 - Computer Basics

• Computers perform a sequence of operations on
  data as specified by a set of instructions
• The Central Processing Unit (CPU) contains the
  Datapath and instruction execution Control Unit
• Instructions and data are stored in Memory
• I D Memory may shared or separate

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Chapter 10 (cont.)

• Datapaths are defined by
• Register set
• Micro-operations
• Control
• Data manipulation performed in the Arithmetic
  Logic Unit (ALU)
• Arithmetic operations
• Logic operations
• Shift operations

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Chapter 10 (cont.)

• The DATA PATH CONTROL WORD defines interface
  between datapath and control unit
• Specifies the microoperation(s) the datapath is
  to perform
• Horizontal discrete bits to select source/dest.
  Registers and functions
• Many bits but more flexible (also dangerous)
• Vertical Each possible register transfer is
  assigned a binary code
• Only a few bits needed but more restrictive
• Most systems use a combination of encoded and
  discrete bit fields for control word

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Chapter 11 - Instruction Set Architecture

• Computer instructions are composed of the
  following fields
• Opcode specifies the instruction operation
• Address either a register or memory address
• Mode how the address/register is used
• Opcode must be present
• Address/Mode define operand location or the
  Effective Address (EA)

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Chapter 11 (cont.)

• Instruction Execution Sequence
• FETCH
• Fetch instruction from memory
• Decode the instruction
• EXECUTE
• Locate operands
• Read operands
• Perform specified operation
• Send result to correct destination
• AND REPEAT

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Chapter 11 (cont.)

• Register Sets
• The programmers register set are those registers
  accessible by the programmer
• The designers register set are all possible
  registers including any special purpose or
  temporary registers
• A superset of the programmers view

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Chapter 11 (cont.)

• Operand Addressing
• Determines the number of operand locations that
  must be determined
• Defined in operand address fields
• 0 - implied addressing
• 1 - Single operand I.e. CLR R0 or NOT R1
• 2 - Two operand one operand is both source and
  destination (binary ops) or just dest.
• 3 - Three operand only used with binary
  operations where a unique output value is
  desired.
• 4 - Four operand Three operand next instruction

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Chapter 11 (cont.)

• Operand location is specified by mode, register
  and address
• The eight basic addressing modes are
• Implied Register direct
• Register indirect Immediate
• Memory direct Memory indirect
• Relative Indexed
• Effective Address - Where the operand is located

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Chapter 11 (cont.)

• Last-In-First-Out (LIFO) Stacks
• Work like plate stacker in cafeteria
• Last item put onto stack is the first one we
  remove
• LIFO stacks usually implemented in main CPU
  memory
• A special register, the stack pointer (SP)
  contains the address of the current Top-Of-Stack
  (TOS)
• Stacks and grow up or down in main memory
• Basic transfer operations are PUSH and POP
• Data manipulation instructions can be zero address

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Chapter 11 (cont.)

• Stack Operations
• PUSH - put data onto stack
• POP - take data of of stack

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Chapter 11 (cont.)

• Program Control Instructions
• Primary characteristic is that they either change
  the PC or affect how the PC is changed
• Conditional JUMP/BRANCH test DP status
• C, N, Z, V bits tested individually or in groups
• Processor Status Word (PSW) or Register (PSR) is
  the collection of status (and other) bits
• CALL saves the current PC (next instruction),
  usually on a LIFO stack before jump to subroutine
• RETURN pops return address off of stack
• EA for Branch instructions is usually relative

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Chapter 11 (cont.)

• Interrupts are effectively externally initiated
  CALLs
• Three types External or Hardware, Internal or
  Exceptions, and Software
• Interrupt condition is checked just prior to
  instruction FETCH
• Both PC and PSR are saved before start of
  Interrupt Service Routine (ISR) execution
• Interrupt return (IRET) restores PC and PSR

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Chapter 13 I/O Communications

• I/O interfaces usually separated into the
• Bus and Interface Unit
• Provides the control, status and data transfer
  functions between CPU data bus and I/O digital
  information
• Adapts CPU data rates to I/O device data rates
• I/O signal conditioning circuitry
• Translates to/from external world representation
  to binary representation
• Must handle problems such as noise, loading,
  voltage translation, A/D, D/A converstion, etc.

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Transfer Modes

• Program controlled transfer
• Software must constantly poll I/O device if ready
• Software then transfers data to/from I/O device
• Interrupt initiated transfer
• Software start data transfer operation
• I/O device interrupts CPU when done
• Software then transfers data to/from I/O device

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Transfer Modes (cont.)

• Direct Memory Transfer (DMA)
• Software starts data transfer
• I/O device moves data directly to/from system
  memory
• I/O device interrupts CPU when done
• I/O Processor (IOP) Data Transfer
• Software sends IOP a set of I/O transfer commands
  for multiple I/O operations
• IOP completes each operation and DMAs data
• I/O device interrupts CPU when done