Introduction to Digital Design 55:032

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Introduction to Digital Design55032

• Exam 2 Review

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General Information

• 1 hour exam - open book, open notes
• Six problems
• Covers material in chapters 4 - 5 of text
• Main focus is on sequential circuit design
• State diagrams
• State tables
• FF input equations
• No VHDL on exam

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Chapter 4 Arithmetic Functions

• Iterative Circuits composed of a series of
  (usually) identical function cells with
  information passed from cell to cell
• Binary Full Adder carry out to carry in
• Useful for implementing large multi-bit vector
  functions
• Binary Adders half and full
• Multi-bit Adders ripple carry

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Chapter 4 (cont.)

• Binary Subtraction
• Subtraction by complements ( A -B)
• Half and Full Subtractor cells
• Adder/Subtractor Circuits
• Overflow
• Result is outside of range of represented values
• MSB carry in not equal to carry out

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Chapter 4 (cont.)

• Other Arithmetic Functions
• Comparison
• Increment
• Decrement
• Increment/Decrement can be implemented by
  contraction
• Start with full adder/subtractor cell
• Fix one set of inputs to constant values
• Generate reduced set of equations

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Chapter 5 Sequential Logic

• Sequential Circuits
• Block Diagram

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Chapter 5

• Binary Storage Elements
• Cross-coupled NOR and NAND latches
• Gated Latch
• Master-Slave Flip-flop
• Edge-Triggered FF
• Input configurations
• SR, JK, D, T
• Characteristic tables
• Direct set/reset inputs
• Table 5-8, Page 248 in the text!!

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Chapter 5 (cont.)

• Sequential Circuit Analysis
• Start with schematic of circuit
• A) Determine FF input and circuit output
  equations
• B) Generate FF transition table
• C) Reorganize as state table
• D) Draw state diagram
• Two basic Seq. circuit forms
• MOORE outputs function of present state only
• MEALY outputs function of both P.S. and inputs

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Chapter 5 (cont.)

• Sequential Circuit Design
• Reverse of Analysis process except we start with
  statement of what circuit is to do
• A) Generate state diagram
• B) Translate to state table (encode inputs,
  states)
• C) Pick FFs to use for state variables
• D) Using FF excitation tables, generate trans.
  table
• E) Generate FF input and circuit output equations