Introduction to Digital Design 55:032

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Introduction to Digital Design55032

• Exam 2 Review

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General Information

• 1 hour exam - open book, open notes
• Six problems
• Covers material in chapters 5 - 8 of text
• Main focus is on sequential circuit design and
  register transfers
• State diagrams
• State tables
• FF input equations
• No VHDL on exam

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Chapter 5 Arithmetic Functions and Circuits

• Iterative combinational circuits
• Binary adders half and full, ripple carry, carry
  lookahead
• Binary subtraction complements
• Binary Adder/Subtractors signed binary numbers
• Binary multiplication
• Other Arithmetic functions increment, decrement,
  comparison
• Skip 5-7 thru 5-9

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Chapter 6

• Binary Storage Elements
• Cross-coupled NOR and NAND latches
• Gated Latch
• Master-Slave Flip-flop
• Edge-Triggered FF
• Input configurations
• SR, JK, D, T
• Characteristic tables
• Direct set/reset inputs

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Chapter 6 (cont.)

• Sequential Circuits
• Block Diagram

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Chapter 6 (cont.)

• Sequential Circuit Analysis
• Start with schematic of circuit
• A) Determine FF input and circuit output
  equations
• B) Generate FF transition table
• C) Reorganize as state table
• D) Draw state diagram
• Two basic Seq. circuit forms
• MOORE outputs function of present state only
• MEALY outputs function of both P.S. and inputs

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Chapter 6 (cont.)

• Sequential Circuit Design
• Reverse of Analysis process except we start with
  statement of what circuit is to do
• A) Generate state diagram
• B) Translate to state table (encode inputs,
  states)
• C) Pick FFs to use for state variables
• D) Using FF excitation tables, generate trans.
  table
• E) Generate FF input and circuit output equations

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Chapter 6 (cont.)

• Going from problem statement to state diagram,
  ASM chart is the hardest part of sequential
  circuit design
• Determine your initial state (reset, idle, etc.)
  where the circuit is waiting for something new
• For each input combination, does the condition of
  the circuit change
• If YES and the condition is new, a new state is
  needed
• If YES and the condition is already a defined
  state, go there
• Otherwise stay at the current state
• For n inputs, you must have 2n transitions!

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Chapter 6 (cont.)

• For generating the flip-flop input values, refer
  to the excitation tables on p. 283 of the text.
• For each Q(t), Q(t1) pairs, translate to the
  flip-flop input values needed for the transition

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Chapter 7 Registers and Reg. Transfers

• Registers
• Registers are groups of flip-flops with some
  common characteristics
• common clock and/or controls
• common data function (counters, storage reg.)
• There are two ways to control when a register
  changes state
• Synchronous enable controls the FF inputs
• Clock gating enable is ANDed with clock

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Chapter 7 (cont.)

• Register transfers and RTL
• More formalized method of describing information
  processing and flow in a system
• General form is
• condition destination ? source expression
• Source expression operations classified as
  transfer, arithmetic, logical, and shift
• A transfer is expected to complete at the next
  clock transition where the condition is true

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Chapter 7 (cont.)

• Register Transfers and RTL
• Elementary register transfer operation are
  microoperations
• Define data sources and function
• Define transfer destination
• Generally assumed to complete in one clock cycle

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Chapter 7 (cont.)

• Micro-operations are combinational logic
  functions
• Transfer, Arithmetic, Logical, Shift
• Many datapaths have a multifunction ALSU to
  perform these operations
• Some datapaths have only enough logic to perform
  a specific set of u-ops

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Chapter 7 (cont.)

• Data Transfer
• Registers may have multiple data sources we must
  select
• Multiplexers
• Dedicated or shared
• Data busses
• Memory transfers need both address and data
  information
• Both source (READ) and destination (WRITE)

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Chapter 7 (cont.)

• Data Transfer may be parallel or serial
• Parallel all data bits moved from register to
  register at the same time (one clock period)
• Faster
• more wiring needed
• Serial data bits move from source register to
  destination register one bit at a time (n clocks)
• need P. to S. and S. to P. shift registers
• only one signal needed

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Chapter 7 (cont.)

• Bidirectional Data Transfer
• Single signal used to send and receive data
• Solves distributed multiplexing problem
• Cuts total number of data lines in half
• Three-State Output Buffers
• Needed to implement bidirectional signals
• Three states are high (1), low (0) and off (hi-z)
• Output Enable signal controls output on or off

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Chapter 7 (cont.)

• Counter is a sequential circuit that cycles
  through a defined set of states
• Synchronous
• Ripple
• Many different variations
• binary, decimal, other sequence
• up, down, or both
• parallel load, clear, enable, ripple carry out
• A counter with no inputs is an Autonomous
  sequential circuit

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Chapter 7 (cont.)

• Arbitrary count sequences
• Classic sequential circuit design
• Define state diagram go from there
• Must ensure unused states have path to normal
  count sequence
• Controlled standard counter
• Detect max value clear counter
• Use carry out signal to load initial count value

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Chapter 7 (cont.)

• Ring and twisted ring counters
• Both use shift register as basic element
• Ring feeds back SR true output to input
• For n FFs there are n states
• Must initialize counter to 00001
• Must handle unused states
• Twisted ring feeds back SR false output to input
• For n FFs there are 2n states
• Counter can be initialized to all zeros (cleared)

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Chapter 8 - Sequencing and Control

• The Control Unit (CU) ensures that the correct
  sequence of micro-operations is performed by the
  DataPath Unit (DPU)
• The sequence of CU states corresponds to the
  sequence of DPU control words.
• The DPU status bits are tested by the CU to
  determine the CU next state transitions.
• CUs are just sequential circuits just more
  complex especially for computer CUs

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Chapter 8 (cont.)

• Algorithmic State Machine (ASM) charts are
  another way to document CU operation
• Each state is defined by an ASM block
• Each ASM block is defined by the following ASM
  elements
• State Box (mandatory) - captures state name and
  any Moore-type outputs and the optional state
  code
• Decision Box - tests inputs to determine next
  states and possible conditional outputs
• Conditional Output Box - defines any conditional
  Mealy outputs

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Chapter 8 (cont.)

• Hardwired CUs are generally faster than
  micro-programmed CUs but less flexible and harder
  to design and modify
• Primarily used when CU is relatively simple and
  task is fixed
• Hardwired CU types are
• Classical Sequential Circuits
• One FF per state (One Hot)
• Sequence register and decoder (not covered)