Pipelining Speeding Up the CPU

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Pipelining Speeding Up the CPU

• 55032 - Introduction to Digital Design

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The Basics of the Problem

• CPU (or any sequential circuit) clock rate is
  limited by maximum clock-to-clock delay

Reg. Prop. Delay C.L. Prop. Delay
Reg. Setup Time
SRCReg.
Combinational Logic
DSTReg.
Clock
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Solution Reduce Clock-to-Clock Delay

• We may not be able to speed up the logic BUT we
  can break it up
• Insert registers into overall signal path
• Shortens the clock-to-clock delay
• Clock can be higher frequency
• It will still take at least as much time to get
  data from one end to the other
• Multiple operations can be in the pipeline at the
  same time

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Pipelined Datapaths
12 ns total clock-to-clock delay Fmax 83.3 MHz
5 ns max total clock-to-clock Delay Fmax 200
MHz
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Pipelined Processing

• Improvement is 3.4 x of single-cycle CPU
• Pipeline must be full
• Data hazards are a problem