CS 162 Computer Architecture Lecture 1

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CS 162 Computer Architecture Lecture 1

• Instructor L.N. Bhuyan
• www.cs.ucr.edu/bhuyan/cs162

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Instructor Information

• Laxmi Narayan Bhuyan
• Office SURGE 319
• E-mail bhuyan_at_cs.ucr.edu
• Tel [phone]
• Office Times W, Th 2-3 pm

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Course Syllabus

• Advanced processor design CPU pipelining,
  Datapath and Control Design, Data and Control
  Hazards The topics will be covered from Chapter
  6 of the text
• Instruction level parallelism, Dynamic scheduling
  of instructions, Branch Prediction and
  Speculation From reference book and papers
• VLIW, Multithreading, and Network processor
  architectures From papers
•  Basic multiprocessor design Shared memory and
  message passing Network topologies. The topic
  will be covered from Chapter 9 of the text.
• Main Text Patterson and Hennessy, Computer
  Organization and Design, Morgan Kaufman Publisher
  
• Reference Hennessy and Patterson, Computer
  Architecture A Quantitative Approach, Morgan
  Kaufman Publisher
• Laboratory Assignments
• (1)  Design of ILP-based processor using
  SimpleScalar (www.simplescalar.com)
• (2) Simulating Intel IXP 1200 network processor
  using SDK simulator
• (3) Performance measurement of IXP 1200-based
  router

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Course Details

• Prerequisite CS 161 with a grade C or better
• Grading Based on Curve
• Test1 25 points
• Test 2 30 points
• Lab 30 points
• Project 15 points

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Review of CS 161

• What is a von-Neumann computer? gt The Stored
  Program Concept Sequential Execution of a
  program instructions in binary for storing in
  memory
• Design of an Instruction Set - RISC Vs. CISC,
  Examples
• Design of CPU Datapath
• CPU Control Design (Hardwire vs.
  Microprogramming)
• Memory Design (Main memory, Cache Memory, Virtual
  memory)
• Input-Output

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MIPS ISA

• 1. all MIPS instructions are same length
• simplifies fetch and decode (steps 1,2)
• Intel 80x86 and IBM 360/370 instructions are
  variable length, 1-17 bytes
• 2. few instruction formats in MIPS
• source register fields are same place in all
  instructions
• can read two registers and decode instruction in
  the same cycle
• Explicit Load/Store instructions for
  memory-register operations

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Review of CPU Datapath Design

• Instruction operation consists of 5 parts,
  namely, Fetch (IF), Decode (ID), Execute (EX),
  Memory (DM), and Write-back (WB) stages
• Single Cycle Design Big Cycle CPI 1
  Problems (1) Low frequency meaning less number
  of instructions executed per cycle (2) All instns
  take same one big cycle
• Multicycle Design Small Cycle CPI lt 5 Break
  the datapath to several stages, each taking one
  cycle. Frequency is increased and some instns can
  finish earlier. Problems Need extra registers to
  separate the stages and control must ensure that
  right control signals must be applied to right
  stage at the right time gt complex control
  design, but still manageable in hardware.

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Review Datapath for MIPS
Stage 5
Instruction Memory (Imem)
Data Memory (Dmem)

• Use datapath figure to represent stages

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Pipelined Execution IPC 1
Time
IFtch
Dcd
Exec
Mem
WB
IFtch
Dcd
Exec
Mem
WB
IFtch
Dcd
Exec
Mem
WB
IFtch
Dcd
Exec
Mem
WB
Program Flow

• To simplify pipeline, every instruction takes
  same number of steps, called stages
• One clock cycle per stage

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Graphical Pipeline Representation
Time (clock cycles)
I n s t r. O r d e r
Reg
DM
Reg
Load
IM
Reg
DM
Reg
Add
Reg
DM
Reg
Store
IM
Reg
DM
Reg
Sub
Reg
DM
Reg
Or
(right half highlighted means read, left half
write)
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Example Single-cycle vs. Pipelined
DM
ALU
IM
Reg
Reg
123
DM
ALU
IM
Reg
Reg
ALU
IM
Reg
time
2 4 6 8
10 12 14
16 18 20
1 2 3
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Advanced Architectural Concepts

• Can we achieve CPI lt 1? (i.e., can we have IPC gt
  1?) State-of-the-Art Microprocessor
• Superscalar execution or Instruction Level
  Parallelism (ILP)
• Deeper Pipeline gt Dynamic Branch Prediction gt
  Speculation gt Recovery
• Out-of-order Execution gt Instruction Window
  and Prefetch gt Reorder Buffers
• VLIW Ex Intel/HP Titanium

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Instruction Level Parallelism (ILP) IPC gt 1
Time
IFtch
Dcd
Exec
Mem
WB
Dcd
WB
IFetch
Exec
Mem
Mem
WB
Exec
IFtch
Dcd
WB
Exec
Dcd
Mem
IFtch
Exec
WB
Dcd
IFtch
Mem
Program Flow ILP 2
EX Pentium, SPARC, MIPS 10000, IBM Power PC
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Very Large Instruction Word (VLIW) IPC gt 1
Time
IFtch
Dcd
Exec
Mem
WB
Exec
Exec
WB
Exec
Dcd
Mem
IFtch
Exec
Program Flow EX Itanium