Sequencing and Control, Part II

1
Sequencing and Control, Part II

• Anselmo Lastra

2
Test 2

• On Tuesday, March 30
• Cover sequential circuits, datapaths, control

3
Homework Posted

• Due next Thursday
• Help review for test 2

4
Topics

• Still on Chapter 8
• Last time
• Hardwired control
• Now
• Microprogrammed control of multiplier
• Overview of lab

5
Microprogrammed Approach

• Control values stored in a memory
• Job of instructions is to generate control
  signals to datapath and output

6
Nomenclature and Characteristics

• Word of memory called microinstruction
• The set of instructions called microprogram
• Sometimes in ROM, sometimes loadable
• Often wide word

7
Recall Datapath
8
Microprogrammed Control Unit

• Control Address Register (CAR) equivalent to PC
• Sequencer
• Part of instruction sent to next-address
  generator to determine next instruction addr

9
Control Data Register

• Pipelining approach to break up the delay in the
  addr gen and ROM
• Not used in example

10
Status Bits

• Notice that they go only to sequencer
• Can only affect next control word
• So, conditional output boxes not allowed in this
  architecture

11
ASM old vs. new
12
Microinstruction

• Word format
• Addresses of potential next instructions
• Fields for next instruction selection
• Fields for datapath control

13
Datapath Control Signals

• Doesnt include load reg inst.
• Look at ASM to see where they are asserted

14
Mapping to Microinstruction

• Have only 4 signals
• Could encode (2 bits?)
• Would cost a decoder
• Just a design tradeoff
• This design has tiny ROM anyway

15
Sequencer Design

• Probably most important part of this process
• This design provides 2 addrs
• SEL field and control logic choose one
• Other possibility is one addr field
• Choice is to go to next sequential addr (like
  PC), or
• Using control signals go to addr specified

16
SEL Field
17
Result

• 5 words in ROM
• ROM is 12 bits wide
• Design next

18
Microprog Design for Mult
Mux chooses addr1 or addr2
Mux control from datapath status and external
signals. Next slide
19
Detail of Control
20
Microprogram
21
Out of Style

• Microprogramming less useful now that HLLs used
  for design
• Can use Verilog to generate very complex state
  machine

22
Lab

• Most of you have this working
• Actually more also memory/control

23
Lab this Week

• This week implement the lw and sw instructions.
• The address for lw/sw generated by ALU
• Format
• sw r1, 100(r2)
• Store contents of register 1 to
• address r2 100

24
Block Diagram (just lw/sw)
25
R-Type and lw/sw
26
Store Word

• Easier
• Just disable writing to register
• Set an address and write to memory
• Could use second memory port and write on same
  cycle as next instruction
• However,

27
Load Word

• Need to determine memory address
• Using ALU
• Then need to read memory
• and write to register

28
Careful

• If you use one memory port, your instruction will
  disappear
• You could use the other memory port
• Could add an instruction register
• More complex control

29
Sign Extension

• Dont get sidetracked into complexity
• Just extend value of bit 15 to upper 16 bits
• How?

30
Next Weeks Lab

• Add beq (branch on equal)
• That should give enough breadth to actually write
  full programs

31
Resulting MIPS Datapath
32
With Control
33
Summary of Next Labs

• This week lw and sw
• Next week beq
• Complete CPU
• Add VGA, keyboard
• April 9 is a holiday
• April 16 free for demo development
• April 23 is the last lab -- Demo

34
Today

• Looked at ways to implement microprogrammed
  control for the multiplier
• Lab overview

35
Next

• Look at computer
• Well also return to look at programmable logic
• Wed skipped earlier