ECE 425 VLSI Circuit Design

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ECE 425 - VLSI Circuit Design

• Lecture 5 - More about Layout
• Spring 2005

Prof. John NestorECE DepartmentLafayette
CollegeEaston, Pennsylvania 18042nestorj_at_lafayet
te.edu
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Announcements

• Homework due Friday 2/18
• 2-2, 2-5, 2-6, 2-7, 2-8, 2-9, 2-12, 2-13, 2-20
• Problem 2-13 hints
• Assume VDD / p-transistors in top half,
• Gnd / n-transistors in bottom half
• Entrance Exam due Friday 2/18
• Reading
• Wolf 2.1-2.6, 3.1-3.4
• Engineering Recruiting Day Fri. 4/1 in
  Philadelphia
• Submit resumes to Career Services by Feburary 25

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Where we are...

• Last time
• Latchup
• Stick Diagrams
• Today
• More about design rules (Lecture 4 notes)
• More about Magic (Lecture 4 notes)
• Hierarchical Stick Diagrams
• Cell Connection Schemes, Example
• Scaling
• The ITRS

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Aside - About MOSIS

• MOSIS - MOS Implementation Service
• Rapid-prototyping for small chips
• Multi-project chip idea - several designs on the
  same wafer
• Reduced mask costs per design
• Accepts layout designs via email
• Brokers fabrication by foundries (e.g. AMI,
  Agilent, IBM, TSMC)
• Packages chips ships back to designers
• Our designs will use AMI 1.5µm process (more
  about this later)

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Aside - About MOSIS

• Some Typical MOSIS Prices (from www.mosis.org)
• AMI 1.5µm Tiny Chip (2.2mm X 2.2mm) 1,130
• AMI 1.5µm 9.4mm X 9.7mm 18,880
• AMI 0.5µm 0-5mm2 6,500
• TSMC 0.25µm 0-10mm2 18,600
• TSMC 0.18µm 0-7mm2 30,000
• IBM 0.13µm 0-10mm2 57,000
• MOSIS Educational Program (what we use)
• AMI 1.5µm Tiny Chip (2.2mm X 2.2mm) FREE
• AMI 0.5mm Tiny Chip (1.5mm X 1.5mm) FREE

sponsored by MOSIS, AMIS, Inc., and IBM
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Layout Considerations

• Break layout into interconnected cells
• Use hierarchy to control complexity
• Connect cells by
• Abutment
• Added wires
• Key goals
• Minimize size of overall layout
• Meet performance constraints
• Meet design time deadlines

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Hierarchy in Layout

• Chips are constructed as a hierarchy of cells
• Leaf cells - bottom of hierarchy
• Root cells - contains overall cell
• Example - hypothetical UART
• Pad frame - ring that contains I/O pads
• Core - contains logic organized as subcells
• Shift register
• FSM
• Other cells

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Hierarchy Example

• Root Cell UART

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Hierarchical Stick Diagrams

• Define cells by outlines use in a hierarchy to
  build more complex cells

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Cell Connection Schemes

• External connection - wire cells together
• Abutment - design cells to connect when adjacent
• Reflection, mirroring - use to make abutment
  possible

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Example 2-input multiplexer

• First cut

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Refined Mux Design

• Use NAND cell as black box
• Arrange easy power connections
• Vertical connections for allow multiple bits

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Multiple-Bit Mux
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Cell Mirroring, Overlap

• Use mirroring, overlap to save area

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Scaling Design Rules

• Effects of scaling down are positive
• See book, p. 78-79 - if everything scales,
  scaling circuit by 1/x increases performance by x
• Problem not everything scales proportionally
• Dielectric thickness tox
• Power supply VDD
• Interconnect
• International Technology Roadmap for
  Semiconductors (ITRS) - see www.itrs.net

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Scaling Transistors

• What is the impact of scaling transistor
  dimensions by a factor of 1/x?
• Constant field scaling (book, from Dennard 74)
• Scale all dimensions by 1/x
• Scale doping concentrations by 1/x
• Scale supply voltage, threshold voltages by 1/x

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Constant-Field Scaling (contd)

• Effect on drain current in saturation
• Effect on gate capacitance
• Effect on circuit speed (time constant CV/I)

Bottom line speedup of 1/x!
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Transistor Scaling

• See Handout Transistor Scaling Section (4.9.1)
  ofN. Weste and D. Harris, CMOS VLSI Design, 3rd.
  Ed.
• Alternative scaling Lateral scaling or Gate
  shrink
• Summary - see WH table 4.15

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Scaling Interconnect

• See Handout Scaling Sections (4.9.2) fromN.
  Weste and D. Harris, CMOS VLSI Design, 3rd. Ed.
• Types of scaling constant-field vs. constant
  thickness
• Summary - see WH table 4.16
• Bottom line interconnect delay gets worse with
  scaling

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Coming Up

• The ITRS Roadmap
• Overview - VLSI Design Flow Tools
• ASIC Layout Styles Economics
• More about CMOS Gate Design