Instruction Set Architecture Part 2

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Instruction Set ArchitecturePart 2

• Lecture 19

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Programmers Model
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Simplified Datapath
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Instruction Formats
The Program Counter (PC) must have its 2 LSBs
00 to ensure 32-bit word alignment.
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Arithmetic Instructions
add t0,s0,s1 set t0 ) (s0)(s1)
sub t0,s0,s1 set t0 ) (s0)-(s1) and
t0,s0,s1 set t0 ) (s0)?(s1) or
t0,s0,s1 set t0 ) (s0)?(s1) xor
t0,s0,s1 set t0 ) (s0)?(s1) nor
t0,s0,s1 set t0 ) ((s0)?(s1))?
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Arithmetic with an Immediate Operand
An operand in the range -32 768, 32 767, or
0x0000, 0xffff, can be specified in the
immediate field. addi t0,s0,61 set t0 )
(s0)61 andi t0,s0,61 set t0 )
(s0)?61 ori t0,s0,61 set t0 )
(s0)?61 xori t0,s0,0x00ff set t0 )
(s0)? 0x00ff
Error Assume that the immediate operand is
sign-extended in ALL FOUR instructions. This is
consistent with the DataPath given on page 248
BUT is not consistent with the middle paragraph
on page 90.
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Loading Registers.
The Offset is sign-extended before adding to the
Base Register Value.
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Load and Store
lw t0,40(s3) load mem40(s3) in t0
sw t0,A(s3) store (t0) in
memA(s3) (s3) means content of
s3 lui s0,61 The immediate value 61 is
loaded in upper half of s0
with lower 16b set to 0s
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Jump Instructions
Unconditional jump and jump through register
instructions j verify go to mem loc
named verify jr ra go to address
that is in ra ra may hold a
return address
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Conditional Branch Instructions
Conditional branches use PC-relative addressing
bltz s1,L branch on (s1)lt 0 beq
s1,s2,L branch on (s1)(s2) bne
s1,s2,L branch on (s1)?(s2)
The signed offset is multiplied by 4 to guarantee
long-word alignment
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Comparison Instructions
slt s1,s2,s3 if (s2)lt(s3), set s1 to
1 else set s1 to 0 often
followed by beq/bne slti s1,s2,61 if
(s2)lt61, set s1 to 1 else set s1 to 0
Look at the MUX at the output of the ALU given on
page 192.
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Addressing Modes
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20 MicroMIPS Instructions