Instruction Set Architecture

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Chapter 10

• Instruction Set Architecture

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10-1 Computer architecture concepts

• Machine language binary language
• Assembly language symbolic language
• In the past, architecture, organization and
  hardware are used to descript a computer.
• Due to the higher and higher performance of
  computer, the relationships among architecture,
  organization and hardware become interwined.
• Instruction set architecture (ISA) is then used
  to encompass the whole of computer.

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10-1 Computer architecture concepts

• The format of an instruction is divided into
  groups called fields as follows.
• opcode field
• address field
• mode field
• The steps for executing an instruction
• Fetch the instruction
• Decode the instruction
• Locate the operand
• Fetch the operand (if necessary)
• Execute the operation in processor registers
• Store the results
• Go back to step 1

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10-1 Computer architecture concepts

• Program counter (PC) keeps track of the
  instructions in the program stored in memory.
• Register set
• Register files in chap. 9 processor status
  register (PSR) stack pointer (SPP

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10-2 Operand addressing

• Three-address instructions (pages 518-519)
• Use mainly memory
• Use mainly register
• Two-address instructions (page 519)
• One-address instructions (pages 519-520)
• A register called accumulator (ACC) is necessary.
• Zero-address instructions (pages 530-521)
• Use a stack
• Last-in, first-out (LIFO)
• Use push and pop instruction
• TOS top of stack

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Addressing Architecture

• Memory-to-memory
• PC is the only register
• 21 accesses to memory needed in the previous
  example (includes accesses of address, data,
  instruction)
• instruction count is low, but the execution time
  is potentially high

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Addressing Architecture

• Register-to-register
• allow only one memory address
• restrict its use to load and store type
• needs sizable register file
• see the program on the top of page 522 in
  textbook
• only 18 memory accesses are needed

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Addressing Architecture

• Register-memory type
• ADD R1, A R1? R1MA
• program lengths and number of memory accesses
  tend to be intermediate between the previous two
  architectures
• Single-accumulator architecture
• no register file
• significant additional memory accesses would be
  needed for complex programs
• inefficient, is restricted to use in CPUs for
  simple, low-cost applications

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Fig. 10-1

• Stack architecture
• high frequency of memory accesses has made it
  unattractive
• is useful for rapid interpretation of high-level
  language programs

Infix expression (AB) C(DE) Postfix
expression ABCDE
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Fig. 10-2
PUSH A PUSH B ADD PUSH C MUL
PUSH D PUSH E MUL ADD
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10-3 Addressing Mode
Addressing mode The rule for interpreting or
modifying the address field of an
instruction. Effective address The address of
operand produced by the application of the rule
for interpreting or modifying the address field
of the instruction before the operand is actually
referenced.
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Addressing Mode

• To give programming flexibility to user
• To reduce the number of bits in the address
  fields of the instruction

Fig. 10-3
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Addressing Mode

• Implied mode needs no address field, the operand
  is specified implicitly in the definition of the
  opcode. For example, ADD in a stack computer.
• Immediate mode an instruction has an operand
  field rather than an address field (the immediate
  format in Fig. 9-14). For example, ADI in Table
  9-8 or the instruction in address 45 in Table 9-9.

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Addressing Mode

• Register and register-indirect mode
• Register mode the address field specifies a
  processor register (the register format in Fig.
  9-14)
• Register-indirect mode the instruction
  specifies a register in the processor whose
  content gives the address of the operand in the
  memory.
• the address field uses fewer bits to select a
  register than would have been required to specify
  a memory address directly
• For example, the auto-increment mode
• ADD (R1), 3 MR1?MR13, R1 ?R11

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Addressing Mode

• Direct addressing mode the address field of the
  instruction gives the address of the operand in
  memory.

ACC?MADRS
Fig. 10-4
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Fig. 10-5 direct addressing in a branch
instruction
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Addressing Mode

• Indirect addressing mode the address field of
  the instruction gives the address at which the
  effective address is stored in memory. For
  example, in Fig. 10-4, the effective address is
  800 (the operand is the one found in memory at
  address 800)
• Relative addressing mode Effective address
  address part of the instruction contents of PC
  (signed number) (the jump format in Fig. 9-14).
  For example, in Fig. 10-4, the effective address
  500 252 (next address in PC)

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Addressing Mode

• Indexed addressing mode the content of an
  indexed register is added to the address part of
  the instruction to obtain the effective address.
• The indexed register may be a special register in
  CPU or simply a register in register file.
• In the application of array, the distance between
  the beginning address and the address of the
  operand is the index value stored in the register.

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Fig. 10-6 Numerical example

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Table 10-1 Symbolic convention for addressing
mode
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10-4 Instruction Set Architectures

• Reduced Instruction Set Computers (RISCs)
• Simple instruction
• Flexibility
• Higher throughput
• Faster execution
• Complex Instruction Set Computers (CISCs)
• Hardware support for high-level language
• Compact program

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Properties of RISC and CISC

• RISC
• Store/load are the only memory accesses
• Data manipulation instructions are
  register-to-register
• Simple addressing mode
• Instruction formats are all the same length
• Instructions perform elementary operations
• One instruction per cycle (simple instruction)

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Properties of RISC and CISC

• CISC
• Memory access is available to most types of
  instruction
• Many addressing mode (substantial in number)
• Instruction formats are of different lengths
• Instructions perform both elementary and complex
  operations (microinstructions are then necessary0
• Multiple cycle for executing one instruction
  (complex instruction)

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RISC and CISC

• Actual instruction set architecture range between
  those which are purely RISC and those are purely
  CISC.
• There is a basic set of elementary operations
  that most computers include among their
  instruction.
• This chapter will focus on the elementary
  instructions that are included in both RISC and
  CISC
• Data transfer instructions
• Data manipulation instruction
• Program-control instructions

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10-5 Data-transfer instructions
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Stack instructions (push/pop)

• Reside in memory
• Due to the negative effects on performance, a
  stack typically handles only state information
  related to procedure calls/returns/interrupts.
• A register holds the address for the stack is
  called stack pointer (SP).

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Fig. 10-7 Memory stack
A new item is placed on the stack by the push
operation SP ?SP-1 MSP ?R1
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I/O Instruction

• Independent I/O The address ranges assigned to
  memory and I/O port are independent from each
  other.
• Memory map I/O assigns a sub-range of the memory
  addresses for addressing I/O port.
• Didnt need distinct input or output
  instructions.

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10-6 Data-manipulation instructions

1. Arithmetic instructions
2. Logical and bit-manipulation instructions
3. Shift instruction

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Arithmetic instructions
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Logical and bit-manipulation instructions
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Shift instruction