Lecture 2: Instruction Set Architecture ISA

1
Lecture 2Instruction Set Architecture (ISA)

• Prof. Kenneth M. Mackenzie
• Computer Systems and Networks
• CS2200, Spring 2003

Includes slides from Bill Leahy
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Review (1/1)

• Technology changes exponentially
• CS2200 focus on abstractions
• Computation/Storage/Communication
• 5 projects 5 homeworks
• 3 exams
• Prereq quiz (well look at the results at the end
  of the hour)

3
The Plan

• Processors
• Memory
• I/O
• Parallel
• Networking

4
Processorstwo issues

• Instruction set and machine model
• the instruction set architecture or ISA
• Circuit implementation (datapath control)
• the microarchitecture

5
Todaymay spill over to next time

• 1. LC-2200 Instruction set
• 2. Real instruction sets
• historical
• RISC
• 3. Procedure invocation
• Nowadays generally implemented as a set of
  conventions atop the assembly language, not part
  of the language itself!
• Suggested LC-2200 convention
• variations!
• 4. Extended Example

6
Instruction Set Architecture (ISA)
software
instruction set
hardware
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Interface Design

• A good interface
• Lasts through many implementations (portability,
  compatability)
• Is used in many different ways (generality)
• Provides convenient functionality to higher
  levels
• Permits an efficient implementation at lower
  levels

use
time
imp 1
Interface
use
imp 2
use
imp 3
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What do you need in an ISA?

• Some state (registers, memory)
• Some operations on that state (instructions)
• computation arithmetic, logical
• data movement memorylt-gtregisters, if any
• control flow loops, if-then-else
• Some means to do I/O

9
LC-2200 Machine Stateeverything is 32 bits wide
Registers
Memory
16 x 32-bit words
0 zero 1 v0 2 a0 3 a1 4 a2 5
a3 6 a4 7 a5 8 s0 9 s1 10 s2 11
s3 12 k0 13 fp 14 sp 15 ra
0 65535
64K x 32-bit words
PC
32-bit word
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LC-2200 Machine Stateeverything is 32 bits wide
Register 0 is always zero
Registers
Memory
16 x 32-bit words
0 zero 1 v0 2 a0 3 a1 4 a2 5
a3 6 a4 7 a5 8 s0 9 s1 10 s2 11
s3 12 k0 13 fp 14 sp 15 ra
0 65535
64K x 32-bit words
Other registers are general-purpose but have
symbolic names according to their
conventional uses
PC
32-bit word
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LC-2200 Machine Stateeverything is 32 bits wide
Memory contains both the program and data
Registers
Memory
16 x 32-bit words
0 zero 1 at 2 v0 3 a0 4 a1 5
a2 6 a3 7 a4 8 s0 9 s1 10 s2 11
s3 12 k0 13 fp 14 sp 15 ra
0 65535
64K x 32-bit words
PC is initialized to zero so the first
instruction of the program is at word 0
PC
0
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LC-2200 Operations on StateInstructions

• Computation
• Arithmetic ADD, ADDI
• Logical NAND
• Data movement
• load/store LW, SW
• Control Flow
• branch BEQ
• jump-and-link JALR
• Other
• halt HALT

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LC-2200 Instruction Typesall are encoded in
single, 32-bit words
R-type Register-Register
31
28
0
19
20
23
24
27
3
4
OP
RA
RB
unused
RD

• How many possible opcodes?
• How many registers?

• How big an immediate?

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LC-2002 Instruction SetArithmetic instructions
Function
R
add
0000
RD ? RA RB
nand
0001
RD? (RA RB)
R-type Register-Register
31
28
0
19
20
23
24
27
3
4
OP
RA
RB
unused
RD
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LC-2002 Instruction SetArithmetic instructions
Function
R
add
0000
RD ? RA RB
nand
0001
RD? (RA RB)
addi
0010
RB ? RA immediate
I
16
LC-2002 Instruction SetData movement instructions
Function
I
lw
0011
RB ? MEMRA Offset
sw
0100
MEMRA Offset ? RB
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Example
Perform C A B where A, B and C are
variables in memory
start lw a0, A(zero) lw
a1, B(zero) add a0, a0, a1
sw a0, C(zero) A .fill 42 B
.fill 37 C .fill 0
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LC-2002 Instruction Setcontrol flow
Function
I
beq
0101
PC lt- PC 1 immediate
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Example
Loop until register a0 is zero
loop beq a0, zero, break
addi a0, a0, -1 beq zero, zero,
loop break
0x0030 0x53000002 0x0031 0x233fffff 0x0032
0x500ffffd 0x0033
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LC-2002 Instruction Setcontrol flow
Function
I
beq
0101
PC lt- PC 1 immediate
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Example
JALR provides the absolute minimum support
for calling a procedure
foo addi at, zero, bar jalr at,
ra ! ... procedure bar runs ...
beq zero, zero, foo bar jalr ra,
zero
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Example
JALR provides the absolute minimum support
for calling a procedure
foo addi at, zero, bar jalr at,
ra ! ... procedure bar runs ...
beq zero, zero, foo bar jalr ra,
zero
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LC-2002 Instruction Setother
Function
O
halt
0111
Halt processor
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LC-2200 Instructions!

• ADD RD, RA, RB
• NAND RD, RA, RB
• ADDI RB, RA, immed20
• LW RB, immed20(RA)
• SW RB, immed20(RA)
• BEQ RA, RB, immed20
• JALR RA, RB
• HALT

• Whats missing?
• How do you do a NOP?
• How do you subtract?
• How do you branch on an inequality? (e.g. BLT)
• Multiply/divide/shifts
• Data types other than 32-bit words?

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administrivia

• ?

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Real ISAs
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(No Transcript)
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Evolution of Instruction Sets
Single Accumulator (EDSAC 1950)
Accumulator Index Registers
(Manchester Mark I, IBM 700 series 1953)
Separation of Programming Model from
Implementation
High-level Language Based
Concept of a Family
Supercomputers
(B5000 1963)
(IBM 360 1964)
(CDC 6600, Cray 1 1963-76)
General Register Machines
Complex Instruction Sets
RISC
(MIPS,Sparc,HP-PA,IBM RS6000, . . .1987)
(Vax, Intel 432 1977-80)
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ISA Issues

• Registers (or not)
• Data types other than 32-bit words
• bytes
• 16-bit words
• floating point
• Procedure invocation

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Classifying Instruction Sets

• machine number/kind of registers
• 0 (stack machine)
• 1 (accumulator machine)
• small (2-6)
• general registers (e.g. 16, 32 or more)
• of addresses per instruction
• 0 (stack machine)
• 1 (accumulator machine)
• 2 (general registers)
• 3 (general registers)
• of those addresses that can be memory

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LC-2200 Machine Stateeverything is 32 bits wide
Registers
Memory
16 x 32-bit words
0 zero 1 v0 2 a0 3 a1 4 a2 5
a3 6 a4 7 a5 8 s0 9 s1 10 s2 11
s3 12 k0 13 fp 14 sp 15 ra
0 65535
64K x 32-bit words
PC
32-bit word
32
Oldest machines1-address or accumulator
machines
Registers (one)
Memory
Acc
0 65535
32-bit word
64K x 32-bit words
PC
32-bit word
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One Address Machine
1

• a.k.a. Accumulator Machine
• One operand is implicitly the accumulator
• LOAD b ACC ? b
• ADD c ACC ? ACC c
• STORE a a ? ACC

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Stack MachinesExtreme no user-visible
registers
User Registers (none)
Memory
0 65535
64K x 32-bit words
Internal Registers
PC
32-bit word
SP
32-bit word
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Zero Address Machine
0

• a.k.a. Stack Machines
• PUSH b Push b onto stack
• PUSH c Push c onto stack
• ADD Add top two items
• on stack and replace
• with sum
• POP a Remove top of stack
• and store in a
• Examples Burroughs B5000 (1960s), B6700, HP 3000

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IBM 360

• General-purpose register set
• 16 (32-bit) integer registers
• 4 (64-bit) floating-point registers
• Multiple addressing modes, e.g.
• R1 ltR1gt ltR2gt
• R1 ltR1gt MEMltR2gt ltR3gt offsetgt
• GPRs vs stack
• The performance advantage of a pushdown stack
  organization is derived prinicpally from the
  presence of several fast registers, not the way
  they are used or specified -- Amdahl/Blaauw/Brook
  s, 1964

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General-Register Machine State(integer only)
Registers
Memory
16 x 32-bit words
0 1 2 3 4 5 6 7 8 9 10 11 12 13 sp
pc
0 65535
32-bit words
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Two Address Machine
2

• a.k.a. Register-Memory Instruction Set
• One operand may be a value from memory (unlike
  Mips)
• Machine has n general purpose registers
• LOAD 1, b 1 ? Mb
• ADD 1, c 1 ? 1 Mc
• STORE 1, a Ma ? 1
• Examples IBM 360 (1963), DEC PDP-11, Motorola
  MC68000

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AddressingModes
circa 1975
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Instruction Length

• Fixed Length Instruction
• Requires different formats
• Can reduce complexity by making different formats
  as constant as possible
• Variable Length Instruction
• Reduces memory usage

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Three Address Machine
3VAX

• Three operands per instruction
• DEC VAX allowed any operand to be in registers or
  in memory!
• ADD A, B, C whole schmoodle!
• Examples DEC VAX, Intel i432

42
Three Address Machine
3RISC

• a.k.a. Load-Store Instruction Set or
  Register-Register Instruction Set
• Can only access memory using load/store
  instructions
• LOAD 1, b 1 ? Mb
• LOAD 2, c 2 ? Mc
• ADD 3, 1, 2 3 ? 1 2
• STORE 3, a Ma ? 3
• Examples CDC6600 (1964), MIPS/SPARC/PowerPC/HP-PA

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History
Hardware Expensive Memory Expensive Accumulators
EDSAC IBM 701
Hardware Less Expensive Memory Expensive Register
Oriented Machines (2 address) Register-Memory
IBM 360 DEC
PDP-11 Also Fringe Element Stack Machines
Burroughs B-5000 (Banks)
Hardware and Memory Cheap Microprocessors Compile
rs getting good CISC VAX
Motorola 68000 Intel
80x86 RISC Berkley RISC?Sparc
Dave Patterson Stanford MIPS ?SGI
John Hennessy IBM 801
1940 1950
1960 1970
1980 1990
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ISA Issues

• Registers (or not)
• Data types other than 32-bit words
• bytes
• 16-bit words
• floating point
• Procedure invocation

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Byte Addressing

• LC-2200 uses only 32-bit words a memory address
  is the address of a 32-bit word.
• Most machines address bytes in memory and provide
  some way to manipulate 8, 16, 32 and sometimes
  larger quantities.
• MIPS LB/LH/LW ... SB/SH/SW

46
Endian-ness

• If you have a byte-addressed machine and you load
  a 32-bit word from memory, which byte is the
  most-significant??

0 1 2 3 4 5 6 7
0x12
0x34
lb a0, 0(zero) --gt 0x00000012
0x56
0x78
lw a0, 0(zero) --gt 0x12345678
or
0x78563412 ???
0x00
0x37
0x42
0x95
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Endian-ness

• Big-endian SPARC, IBM 360, MC68000
• Little-endian x86, VAX, MIPS (usually)
• A number of embedded processors are switchable
  (e.g. MIPS)
• Example of persistence of bad (or in this case
  inconsequential) interface issues!

48
Floating Point

• Typically implemented as a separate register set
  and separate instructions.

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Procedures

• (deferred to Tuesday)

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Summary

• 1. LC-2200 Instruction set
• 2. Real instruction sets
• historical
• RISC
• 3. Procedure invocation
• Nowadays generally implemented as a set of
  conventions atop the assembly language, not part
  of the language itself!
• Suggested LC-2200 convention
• variations!
• 4. Extended Example