Title: ECE 491 Senior Design I
1ECE 491 - Senior Design I
- Lecture 2 - Verilog Review
- Fall 2004
- Announcement No lab this week
- Handout Structural Design with Verilog (from
last year)Read Sections 1-5
Prof. John NestorECE DepartmentLafayette
CollegeEaston, Pennsylvania 18042nestorj_at_lafayet
te.edu
2Todays Outline
- Overview Electronic Design with FPGAs
- Verilog Review Part 1
- Language Overview
- Combinational Logic
- Continuous Assignment
- Module Instantiation
- always blocks
- Discuss Lab 1
- Overview of the Spartan-3 Starter Kit Board
- Design Problem
3Levels of Abstraction in Design
Specification (what the chip does, inputs/outputs)
Architecture major resources, connections
Register-Transfer logic blocks, FSMs, connections
Logic gates, flip-flops, latches, connections
Circuit transistors, parasitics, connections
Layout mask layers, polygons
4FPGA Design Flow
- Synthesis
- Translate HDL to hardware
- Optimize map to CLBs
- Estimate timing
- Placement
- Map CLBs to specific locations
- Routing
- Determine how to interconnect CLBs
- Program
- Download bitstream into FPGA
5Verilog Review
- Important Points
- Basic Module Syntax
- Combinational Logic
- Parameters
- Module Instantiation
- Sequential Logic
- Finite State Machines
6Important Points about Verilog
- Verilog is designed to model hardware
- Hardware is parallel, so execution is parallel
7Important Points about Verilog (contd)
- Verilog is based on event-driven simulation
- Signal values change at specific timepoints
- Each model
- Activates in response to input events
- Creates output events to represent output changes
8Important points about Verilog (contd)
- Verilog was designed as a simulation language
- Synthesis added as an afterthought
- Only a subset of the language supported for
synthesis - Synthesis must match simulated behavior
- Well focus mostly on the synthesis subset
- Structural Descriptions - module instantiations
- Behavioral Descriptions
- assign - continuous assignments
- always blocks
- But, well use simulation capabilities for
verification - initial blocks
- Delay
9Verilog module construct
- Key building block of language
- declaration - specifies a module interface
- Input output ports connections to outside world
- black box model - no details about internals
- body - specifies contents of "black box"
- behavior - what it does
- structure - how it's built from other "black
boxes"
10Verilog Review - Language Details
- Syntax - See Quick Reference Card
- Major elements of language
- Lexical Elements (tokens and token
separators) - Data Types and Values
- Operators and Precedence
11Verilog Lexical Elements
- Whitespace - ignored except as token separators
- blank spaces
- tabs
- newlines
- Comments
- Single-line comments //
- Multi-line comments / /
- Operators- unary, binary, ternary
- Unary a b
- Binary a b c
- Ternary a (b lt c) ? b c
12Verilog Numbers
- Sized numbers ltsizegt'ltbase formatgtltnumbergt
- ltsizegt - decimal number specifying number of bits
- ltbase formatgt - base of number
- decimal 'd or 'D
- hex 'h or 'H
- binary b or B
- ltnumbergt - consecutive digits
- normal digits 0, 1, , 9 (if appropriate for
base) - hex digits a, b, c, d, e, f
- x "unknown" digit
- z "high-impedance" digit
- Examples
- 4b1111 12h7af 16d255
13Verilog Numbers (cont'd)
- Unsized numbers
- Decimal numbers appearing as constants (236, 5,
15, etc.) - Bitwidth is simulator-dependent (usually 32 bits)
- Negative numbers
- sized numbers '-' before size -8'd127 -3'b111
- unsized numbers '-' before first digit -233
- Underline '_' can be used as a "spacer
- 12'b00010_1010_011 is same as
12'b000101010011
14Verilog Strings
- Anything in quotes is a string "This is a
string" "a / b" - Strings must be on a single line
- Treated as a sequence of 1-byte ASCII values
- Special characters - C-like (\)
15Verilog Identifiers
- Starting character alphabetic or '_'
- Following characters alpha, numeric, or '_'
- Examples george _paul
- "Escaped" identifiers
- start with backslash
- follow with any non-whitespace ASCII
- end with whitespace character
- Examples \212net \xyzzy \foo
- Special notes
- Identifiers are case sensitive
- Identifiers may not be reserved words
16Verilog Reserved Words
- always and assign begin buf bufif0 bufif1 case
- casex casez cmos deassign default defparam disabl
e edge - else end endcase endfunction endmodule
- endprimitive endspecify endtable endtask event for
- force forever fork function highz0 highz1 if ifnon
e - initial inout input integer join large macromodule
- medium module nand negedge nmos nor not
- notif0 notif or output parameter pmos
- posedge primitive pull0 pull1 pulldown pullup rcmo
s - real realtime reg release repeat rnmos rpmos rtran
- rtranif0 rtranif1 scalared small specify specparam
strong0 - strong1 supply0 supply1 table task time tran trani
f0 - tranif1 tri tri0 tri1 triand trior trireg vectored
- wait wand weak0 weak1 while wire wor xnor
- xor
17Verilog Data Types
- nets - describe wire connections
- general purpose wire
- special purpose supply0, supply1, tri0,
tri1, triand, trior, trireg, wand, wor - registers - variables (assigned values by
procedural statement) - reg - basic binary values
- integer - binary word (32 bits - machine
dependent) - real - floating point (not supported by
synthesis) - time - simulation time (not supported in
synthesis) - realtime - simulation time (not supported in
synthesis)
18More about Data Types
- Vectors - Multiple-Bit Signals (net or register)
- wire 310 sum
- reg 70 avg
- Arrays - used for memories
- reg 70 memory 0255
19Verilog Logic Values
- Each wire or register type can take on 4 values
- 0 - Standard binary FALSE
- 1 - Standard binary TRUE
- X - UNKNOWN
- Z - High Impedance
- During simulation, all variables originally X
- Complication x z sometimes used as wildcards
(e.g. casex, casez)
20Operators and Precedence
- Override with parentheses () when needed
21Verilog Module Declaration
- Describes the external interface of a single
module - Name
- Ports - inputs and outputs
- General Syntax
- module modulename ( port1, port2, ... )
- port1 direction declaration
- port2 direction declaration
- reg declarations
- wire declarations
- module body - parallel statements
- endmodule // note no semicolon () here!
22Verilog Body Declaration - Parallel Statements
- Parallel statements describe concurrent behavior
(i.e., statements which execute in parallel) - Types of Parallel Statements
- assign - used to specify simple combinational
logic - always - used to specify repeating behavior for
combinational or sequential logic - initial - used to specify startup behavior (not
supported in synthesis - but useful in
simulation!) - module instantiation - used for structure
- and other features useful only in simulation
23Continuous Assignment - Example
- Full Adder
- module fulladder(a, b, cin, sum, cout)
- input a, b, cin
- output sum, cout
- assign sum a b cin
- assign cout a b a cin b cin
- endmodule
24Comments about the First Example
- Verilog describes a circuit as a set of modules
- Each module has input and output ports
- Single bit
- Multiple bit - array syntax
- Each port can take on a digital value (0, 1, X,
Z) - Three main ways to specify module internals
- Continuous assignment statements - assign
- Concurrent statements - always
- Submodule instantiation (hierarchy)
25Bitwise Operators
- Basic bitwise operators identical to C/C/Java
- module inv(a, y)
- input 30 a
- output 30 y
- assign y a
- endmodule
26Reduction Operators
- Apply a single logic function to multiple-bit
inputs - module and8(a, y)
- input 70 a
- output y
- assign y a
- endmodule
equivalent to a7 a6 a5 a4 a3
a2 a2 a2 a0
27Conditional Operators
- Like C/C/Java Conditional Operator
- module mux2(d0, d1, s, y)
- input 30 d0, d1
- input s
- output 30 y
- assign y s ? d1 d0// output d1 when s1,
else d0 - endmodule
28More Operators
- Equivalent to C/C/Java Operators
- Arithmetic - /
- Comparison ! lt lt gt gt
- Shifting ltlt gtgt
- Example
- module adder(a, b, y)
- input 310 a, b
- output 310 y
- assign y a b
- endmodule
- Warning small expressions can make big hardware
if complex operators are used!
29Bit Manipulation Concatenation
- is the concatenation operator
- module adder(a, b, y, cout)
- input 310 a, b
- output 310 y
- output cout
- assign cout,y a b
- endmodule
30Bit Manipulation Replication
- n pattern replicates a pattern n times
- module signextend(a, y)
- input 150 a
- output 310 y
- assign y 16a15, a150
- endmodule
31Internal Signals
- Declared using the wire keyword
- module fulladder(a, b, cin, s, cout)
- input a, b, cin
- output s, cout
- wire prop
- assign prop a b
- assign s prop cin
- assign cout (a b) (cin (a b))
- endmodule
32Combinational always blocks
- Motivation
- assign statements are fine for simple functions
- More complex functions require procedural
modeling - Basic syntax
- always (sensitivity-list)
- statement
- or
- always (sensitivity-list)
- begin
- statement-sequence
- end
33Combinational Modeling with always
- Example 4-input mux behavioral model
- module mux4(d0, d1, d2, d3, s, y)
- input d0, d1, d2, d3
- input 10 s
- output y
- reg y
- always _at_(d0 or d1 or d2 or d3 or s)
- case (s)
- 2'd0 y d0
- 2'd1 y d1
- 2'd2 y d2
- 2'd3 y d3
- default y 1'bx
- endcase
- Endmodule
34Another Example ALU from ECE 313
- module alu(ctl, a, b, result, zero)
- input 20 ctl
- input 310 a, b
- output 310 result
- output zero
- reg 310 result
- reg zero
- always _at_(a or b or ctl)
- begin
- case (ctl)
- 3'b000 result a b // AND
- 3'b001 result a b // OR
- 3'b010 result a b // ADD
- 3'b110 result a - b // SUBTRACT
- 3'b111 if (a lt b) result 32'd1
- else result 32'd0 //SLT
- default result 32'hxxxxxxxx
- endcase
- if (result 32'd0) zero 1
35Modeling with Hierarchy
- Create instances of submodules
- Example Create a 4-input Mux using mux2 module
- Original mux2 module
- module mux2(d0, d1, s, y)
- input 30 d0, d1
- input s
- output 30 y
- assign y s ? d1 d0
- endmodule
36Modeling with Hierarchy
- Create instances of submodules
- Example Create a 4-input Mux using mux2 module
- module mux4(d0, d1, d2, d3, s, y)
- input 30 d0, d1, d2, d3
- input 10 s
- output 30 y
- wire 30 low, high
- mux2 lowmux(d0, d1, s0, low)
- mux2 highmux(d2, d3, s0, high)
- mux2 finalmux(low, high, s1, y)
- endmodule
37Data Types and Module Ports
- Input ports must always be a wire (net)
- Output ports can be wire or reg
wire
reg
wire
wire
wire
wire
38Parameterized Modules
- Parameters - define values that can change
- Declaration
- module mod1(in1, in2, out1, out2)
- parameter Ndefault-value
- input N-1 0 in1, in2
- output N-1 0 out1
-
- endmodule
- Instantiation
- wire 70 w, x, y
- wire z
- mod1 (8) my_mod1(w,x,y,z)
39Parameterized Modules Example
- N-bit 2-1 multiplexer (parameterized bitwidth)
- module mux2( sel, a, b, y )
- parameter bitwidth32
- input sel
- input bitwidth-10 a, b
- output bitwidth-10 y
- assign y sel ? b a
- endmodule
- Instantiations
- mux2 (16) my16bit_mux(s, a ,b, c)
- mux2 (5) my5bit_mux(s, d, e, f)
- mux2 (32) my32bit_mux(s, g, h, i)
- mux2 myDefault32bit_mux(s, j, k, l)
40Symbolic Constants with Parameters
- Idea use parameter to name special constants
- parameter RED_ALERT 2b11
- parameter YELLOW_ALERT 2b01
- parameter GREEN_ALERT 2b00
- Dont change in module instances
- Do this to make your code more understandable
- For others reading your code
- For yourself reading your code after some time
has passed
41Symbolic Constant Example
- 7-segment decoder from Verilog Handout (Part 1)
- module seven_seg_display_decoder(data, segments)
- input 30 data
- output 60 segments
- reg 60 segments
- // Segment abc_defg hex
equivalent - parameter BLANK 7b111_1111 // h7F
- parameter ZERO 7b000_0001 // h01
- parameter ONE 7b100_1111 // h4F
- parameter TWO 7b001_0010 // h12
- parameter THREE 7b000_0110 // h06
- parameter FOUR 7b100_1100 // h4C
- parameter FIVE 7b010_0100 // h24
- parameter SIX 7b010_0000 // h20
- parameter SEVEN 7b000_1111 // h0F
- parameter EIGHT 7b000_0000 // h00
- parameter NINE 7b000_0100 // h04
42Symbolic Constant Example
- 7-segment decoder from Verilog handout (Part 2)
- always _at_(data)
- case (data)
- 0 segments ZERO
- 1 segments ONE
- 2 segments TWO
- 3 segments THREE
- 4 segments FOUR
- 5 segments FIVE
- 6 segments SIX
- 7 segments SEVEN
- 8 segments EIGHT
- 9 segments NINE
- default segments BLANK
- endcase
- endmodule
43Symbolic Constants using define
- Like C/C, Verilog has a preprocessor
- define - equivalent to define in C/C
- Symbolic constant definition
- define ZERO 7b0000_0001
- Symbolic constant usage preface with
- segments ZERO
- Other preprocessor directives
- ifdef
- else
- endif
44More about always
- Specifies logic with procedural statements
- Simulation model executes statements in order
- Synthesized hardware matches simulation
- reg declarations
- treat like variables in C or Java
- assignment holds value until a new assignment is
made - module my_logic(a, b, c, d)
- input a, b
- output c, d
- reg c,d
- always _at_(a or b) begin
- c a b
- d b c
- end
- endmodule
45Synthesizing Comb. Logic
- When no if, case, or loop statements
- Assignment statements generate logic
- Outputs are values of last assignments
- Logic optimized, reduced during synthesis
- module my_logic(a, b, c, d)
- input a, b
- output c, d
- reg c,d
- always _at_(a or b) begin
- c a b
- d b c
- c d a
- end
- endmodule
46Synthesizing Comb. Logic - if/else
- if/else statements become multiplexers
- multiplexers follow statement order
- always _at_(c or d or x or y) begin
- if (c 1b1) z x y
- else z x - y
- if (d 1b0) w z
- else w x
- end
47Synthesizing Comb. Logic - if /else if / else
- Each else implies mutual exclusion
- if / else if / else creates a priority encoder
- always _at_(c or d or x or y) begin
- if (c 1b1) z x y
- else if (d 0b0) z x - y
- else z x
- end
- Use sequential if statements without else if to
avoid priority if desired
48Synthesizing Comb. Logic - if without else
- if without else output depends on previous value
- always _at_(a or x or y) begin
- w x y
- if (a 1b1) w x
- end
- What if no previous value is specified?
- Must preserve the semantics of the language
- This requires a latch inference
- always _at_(a or x) begin
- if (a 1b1) w x
- end
49Synthesizing Comb. Logic - if without else
(latch inference)
- if without else output depends on previous value
- always _at_(a or x or y) begin
- if (a 1b1) w x
- end
- What if no previous value is specified?
- Must preserve the semantics of the language
- This requires a latch inference to store old
value
50Synthesizing Comb. Logic - case statements
- Verilog case treated as if / else if / else ...
- always _at_(e or x or y) begin
- case (e)
- 2b00 w x y
- 2b01 w x - y
- 2b10 w x y
- default w 4b0000
- endcase
- end
- Use default to avoid latch inference!
51Synthesizing Comb. Logic -One Last Pitfall
- always must include all inputs in sensitivity
list - OR mismatch between synthesis simulation!
- always _at_(e or x) begin
- case (e)
- 2b00 w x y
- 2b01 w x - y
- 2b10 w x y
- default w 4b0000
- endcase
- end
52About Lab 1
- Goals of Lab 1
- Review Combinational Logic Design with Verilog
- Learn about FPGA Design with Verilog
- Learn about the Spartan-3 Starter Kit Board (S3
Board)
53Starter Kit Board - Overview
54S3 Board Seven-Segment Display
- Segment signals - active low
- Digit enables used to time multiplex digits
55Using the S3 Board with Verilog
- Top-level module file s3board.v
- Contains declarations for all input output pins
- Switches pushbuttons
- LEDs and 7-segment displays
- RS-232 port(s)
- Not used (currently) PS/2 port, VGA port
- Use as a starting point for your design
- Constraint file s3board.ucf
- Contains pin assignments for all inputs outputs
- Uncomment pins that youre going to use (remove
) - These files can be downloaded from the website
56What to Do in Lab 1
- Download s3board.v and s3board.ucf
- Run ISE and create a new project
- Add s3board.v and s3board.ucf
- Add Verilog code for a 4-bit adder
- Add Verilog code for a 7-segment decoder with hex
digits - Connect slide switches to adder inputs
- Connect 7-segment decoder to adder output
- Connect 7-segment decoder to display LSB
- Compile, download, debug
57Lab 1 - Block Diagram
58Coming Up
- Sequential Logic Design with Verilog FPGAs
59The remaining slides are under construction
- What are these pitfalls?
- Latch Inference
- Missing inputs on sensitivity list
60Sequential Design in Verilog - Basic Constructs
- Describe edge-triggered behavior using
- always block withedge event
- always _at_(posedge clock-signal)
- always _at_(negedge clock-signal)
- Nonblocking assignments (lt)
- _at_always(posedge clock-signal)
- begin
- output1 lt expression1
- . . .
- output2 lt expression2
- . . .
- end
61Combining Sequential and Combinational Outputs
- General circuit - both registered and comb.
outputs - Approach multiple always blocks or assign
statements
62Example Adding carry to 4-bit Counter
- module counter(clk, Q, carry)
- input clk
- output 30 Q
- output carry
- reg 30 Q // a signal that is assigned a
value - assign carry (Q 4'b1111)
- always _at_( posedge clk )
- begin
- Q lt Q 1
- end
- endmodule
63Review Question What Happens Here?
- module counter(clk, Q, carry)
- input clk
- output 30 Q
- output carry
- reg 30 Q // a signal that is assigned a
value - reg carry
- always _at_( posedge clk )
- begin
- carry lt (Q 4'b1111)
- Q lt Q 1
- end
- endmodule
64State Machine Design
- Traditional Approach
- Create State Diagram
- Create State Transition Table
- Assign State Codes
- Write Excitation Equations Minimize
- HDL-Based State Machine Design
- Create State Diagram (optional)
- Write HDL description of state machine
- Synthesize
65Coding FSMs in Verilog - Explicit Style
- Clocked always block - state register
- Combinational always block -
- next state logic
- output logic
66Coding FSMs in Verilog - Code Skeleton
- Part 1 - Declarations
- module fsm(inputs, outputs)
- input . . .
- input . . .
- reg . . .
- parameter NBITS-10
- S0 2'b00
- S1 2'b01
- S2 2b'10
- S3 2b'11
- reg NBITS-1 0 CURRENT_STATE
- reg NBITS-1 0 NEXT_STATE
-
67Coding FSMs in Verilog - Code Skeleton
- Part 2 - State Register, Logic Specification
-
- always _at_(posedge clk)
- begin
- CURRENT_STATE lt NEXT_STATE
- end
- always _at_(CURRENT_STATE or xin)
- begin
- case (CURRENT_STATE)
- S0 . . . determine NEXT_STATE, outputs
- S1 . . . determine NEXT_STATE, outputs
- end case
- end // always
- endmodule
68Verilog and Event-Driven Simulation
- Key idea model circuit operation as sequence of
events that take place at specific times - Input events - when input changes
- Output events - response to input events (only
generated when output changes)
69Event-Driven Simulation
- Example Modeling and AND Gate
- Input events changes on A, B input net
- Output events changes on C output net after
delay
A
delay12
A
B
C
B
C
70Event-Driven Simulation
- Output events from AND input events for OR
- Simulation time jumps from event to event
A
delay3
B
A
D
delay4
C
B
E
C
D
E
71Notes about Event-Driven Simulation
- Why use event-driven simulation? Because it's
fast - Only model when signals change
- Loss of accuracy assumes ideal logical behavior
- What are the alternatives?
- Circuit simulation (e.g. PSpice)
- Numerical model of continuous behavior
- More accurate, but slower
- Cycle-Level Compiled code simulation
- Model behavior in each clock cycle
- Faster, but doesnt model dlay
72Event-Driven Simulation (cont'd)
- Processing Events - Data Structures
- Event - specifies
- time event will occur
- net where signal will change
- new value of net
- Event Queue - data structure that sorts events by
time - front of queue - earliest event
- back of queue - latest event
- also called a timing wheel
73Event-Driven Simulation - Algorithm
- Processing Events - Simulation Algorithm
- initialization set all nets regs to x
- while (event queue not empty)
current_event "earliest" event in queue
current_time current_event.time
current_event.net.value current_event.value
for (each module input connected to net)
evaluate(module) if output of module
changes create new event to represent
output change add new event to queue
74Verilog Simulation Model
- assign statement
- executes when event changes any input
- produces output event when output values changes
- always block
- executes when event changes variable in
sensitivity list - produces output events when outputs change
75Coming Up
- Delay Modeling in Verilog
- Other Verilog Features
- tasks functions
- system tasks
- Verilog coding styles
- Behavioral Modeling
- Testbenches and Verification
76Course Map