ECE Senior Project

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ECE Senior Project

• CMOS Camera
• System-on-a-Chip
•  

2
TEAM MEMBERS

• Anil Kumar
• Angana Sheth
• Saurabh Desai
• George Moran
• Jason Moffa
• Takashi Ishihara
• ADVISOR Dr. Brita Olson

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CMOS Camera System-on-a-Chip

• A normal camera uses film to save the image that
  hits its lens.
• We are designing a chip that saves the image
  digitally by sensing the amount of light or image
  that each one of its pixel sees.
• The image consists of 128 by 128 pixels there
  are total 16384 pixels.

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PROJECT DIAGRAM
128 x128
5
Design Goals
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Establishing a Chip Design Infrastructure

• Learning VLSI Design
• Learning VLSI Design Tools and Chip Design
  Process
• Establishing a Chip Design Flow at CPP
• Configuring tools

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Progress

• Calculations/Analysis
• Floor Planning Conversion Gain
• Parasitics /Loading Noise
• Component Development
• Design Optimization, Simulation with loading,
  Port to new environment
• Decoder primitive Anti-blooming Circuitry
• Decoder Bus Driver Row driver Row RST SEL
  Driver
• Anti-blooming Circuitry Amplifier Bias Circuitry
• Pixel Analog Signal Chain Sample Hold
  Circuit

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Progress (cont.)

• Chip Level Design
• Pixel Array schematic
• In progress
• 7-bit decoder
• Analog Signal Chain with Correlated Double
  Sampling

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Accomplished Tasks

• Floor Planning
• 7 Bit Decoder
• Anti Blooming Circuitry

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FLOOR PLANNING
Pitch 150um
16 pads

• The floor plan estimates the area of major
• units in the chip and defines their relative
• placements.
• The floor plan is essential to determine
• whether a proposed design will fit in the chip
  area budgeted and to estimate wiring lengths and
  wiring congestion, so an initial floor plan
  should be prepared as soon as the logic is
  loosely defined.
• Pitch It is a distance between two pads.
• Pads They are wired to the pins on the chip
  package. They are for the I/O
  connection on the chip

128128 Imager
16 pads
3mm
13612um
3mm

• 4 AMI 0.5um Tiny Chips
• Packaging 150um pad pitch
• Pixels 12um pitch

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APS Architecture
R O W D R I V E R S
R O W D E C O D E R

• Row Decoder
• Selects row for readout.
• Column Decoder
• Controls readout of
• Pixels In given row.

128128 PIXEL ARRAY
Rowi
128
27128

• A decoder is a Combinational circuit, when
  enabled, produces one of 2n minterms or maxterms
  at the output based on the input Combinations.

READOUT CIRCUITS
128
COLUMN DECODER
27128
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Decoder Implementation
Row-addlt06gt
Row-addlt06gt
0 0 0 0 0 0 0
Selects row 0
1 0 0 0 0 0 0
Selects row 1

• A 7 input nand gate based implementation results
  in a compact and regular realization reducing
  development time and cost.
• The chip that we are designing has 128128 pixels
  so the decoder consists of 128 of 7 input nand
  gates.

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Decoder Design Requirements

• Master Clock 20MHz
• Trise/Fall requirements are relaxed.
• In our design Trise/Fall times are 50 of clock.
• Trise/Fall ½(1/20MHz)
• 25ns

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Schematic of 7-input nand gate

• PMOS Operational W/L
• (W min/L min to 7W min/L min)
• NMOS Operational W/L
• W min/7L min
• Both NMOS PMOS are
• minimum sized transistor
• (W1.05um, L0.7um)
• W/L eff PMOS 1.05/0.7
• W/L eff NMOS 1/7(1.05/0.7)

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Simulation for fall time when W 1.05um
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Simulation for rise time when W 1.05um
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Rise / Fall Time Table
Rise Time Fall Time
W 1.05um 1.46ns 2.709ns
L 0.7um

• Better Trise/Fall times results due to reduced W
• of PMOS transistor.
• Reduced W of transistor results in
• Reduction of power consumption
• Reduction in substrate noise
• Reduction in input capacitance Reduces chip
  area,
• 
  power, noise.

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Anti Blooming Circuitry

• Reduces charge buildup in pixels due to excessive
  illumination
• Prevents flow of excess charge into neighboring
  pixels.
• It does this by redirecting the excess current
  into the anti-blooming drain when the photodiode
  is too full.
• Without anti blooming circuitry imaging artifacts
  will happen.

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Anti Blooming Circuit Operation
Vdd
RST 5V RST_LO 1V VTH 0.7V
RST 5v
RST_LO 1V
Integration

• Normal Imaging Condition
• When RST signal is applied FD is around 2.8V
  and after integration
• of light it becomes 1.8V.
• (Vgs lt VTH) 1 1.8 lt 0.7 -? Transistor Off
• Bright Light
• Due to bright light FD decreases to 0.3V
• (Vgs gt VTH) 1 0.3 gt 0.7 ? Transistor on
  and excess carriers removed.

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Anti Blooming Circuitry
Final stage of row driver
Anti blooming circuitry
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7 BIT INPUT SIGNAL DECODER DRIVER
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Schematics

• Driver (4x8x) Driving a load of 64, CMOS N and P
  transistors.

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Simulations

• Rise Time 6 Fall time 5
• Approximate time is 1 nano second to drive
  signal.

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VALUES GIVEN

• W 1.05uM
• L 0.7uM
• VDD 3.3v

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SCHEMATIC
V5 V4 V0
0 0 VDD
VDD 0 VDD
0 VDD VDD
VDD VDD 0
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SCHEMATIC RESULT
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SYMBOL FOR THE AND GATE
ROW i
RSTi
RST
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Accomplished Tasks

• 1. Determine Resistive and Capacitive Parasitic
  Loading (Caused by
  dimension of the pixel Array)
• 2. Row Driver Design
• -Determine best combination for Drivers
• -Rise and Fall Times
• -Reset Driver
• -Select Driver
• 3. Simulations using PSPICE
• 4. Implementation of Design using Cadence (LINUX)

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Chip Schematic
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Overview of Row Driver
SEL
SELi
ROWi
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Parasitic Loading

• Determination of load resistor
• Determination of Capacitive load

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The Row Driver
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The Row Driver (cont.)
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Simulations Summarized

• Table 1 Rise and Fall Times for Inverter driving
  128 transistors
• (using 102,400,402,600ns Vdd3.3V Cload
  41.4fF)
• Table 2 Rise and Fall times for inverters
  driving inv_8x
• (using 102,400,402,600ns Vdd3.3V Cload
  41.4fF)

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Schematics

• Two Drivers (4x_8x) Driving 128 CMOSN transistors

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Simulations

• Rise/Fall Times

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Row Select Driver Design

• Three Drivers (1x_4x_8x) Driving 128 CMOSN
  transistors

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Row Select Driver Simulation with Loading

• Rise/Fall Times

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Row Reset Driver Design

• Introduction of two different power supply levels

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Simulations

• Rise/Fall Times

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General Chip Layout
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Pixel Timing Diagrams
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Current Mirror Circuit To Bias Pixel SF

• Large gate widths and lengths used
• Good threshold matching
• gm reduced

Current Equation
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Determining Initial Condition For Sample Hold
Capacitor
Pixel
Sample Hold Capacitor
Bias

• Optimize RST signal due to Body Effect

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The Body Effect

• Source ?Body
• Modified threshold voltage

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Initial Condition for Sample Hold Capacitor
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Determining Time to Discharge Sample Hold
Capacitor Within 0.1 Accuracy

• VFD initial condition V 1.8V

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Transient Response of Pixel Discharge
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Determining time to charge sample hold
capacitor Within 0.1 Accuracy
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Transient Response of Pixel Charge
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Accomplishments

• Designing output driver
• Determining the conversion gain
• Designing the pixel array

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Output Driver
Pixel Array
ADC
Analog Sig. Chain
Parasitic Capacitance
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Output Driver Operation
CL 8pF
Vout
Vin
DV 1V
Slewing (25)
Settling (75)
Step function
Ttot 100 .5msec
Slewing small sig. Analysis not
appropriate Settling transistors in saturation
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Schematic
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Settling
Amplifier transfer function
Output
Settling accuracy
Vin
DV 1V
Step function
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Tfall output Driver (35uA)
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Trise output Driver (35uA)
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Slewing and Settling
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Conversion Gain
Miller Effect
Cm
Cm(1-A)
C(total) Cfd Cm(1-A)
V Q/C
C.G. Vout/Number of Electrons
q/C(total)
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Conversion Gain
(3)
W
Gate
4?
Source
Source
4?
(2)
W
(1)
(1) Cj(W4?) (2) Csw(W24?) (3) CswgW Cfd
Cj(W4?) Csw(W24?)CswgW 1.19fF
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Conversion Gain
Vout
0.9
0.9
0.8
C(total)
C(total) CfdCm(1-A) 1.19fF
Input C.G. q/C(total) 134uV/electron Output
C.G. (0.8)(0.9)(0.9)(134u)
87.1uV/electron
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CHIP PROCESS
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Remaining Tasks

• Component development
• Optimization of Analog Signal
  chain with CDS
• Chip Level Schematic Development
• Completion of Decoder
• Pad Ring
• Assembly of final chip schematic
• Full Chip Simulations
• Layout

64
Acknowledgments