ECE 491 Senior Design I

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ECE 491 - Senior Design I

• Lecture 4 - Verilog 2 (Sequential Logic)
• Fall 2007
• Read Verilog Handout Sections 1-6

Prof. John NestorECE DepartmentLafayette
CollegeEaston, Pennsylvania 18042nestorj_at_lafayet
te.edu
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Todays Outline

• Verilog Review Part 2
• Sequential Logic
• Basic Constructs
• Examples
• Registered vs. Combinational Outputs
• Lab 2 - Basic Sequential Logic
• Finite State Machines
• Coding Guidelines
• Discuss Lab 2

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Aside - Great Moments in Lab Notebooks
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Sequential Design in Verilog - Basic Constructs

• Describe edge-triggered behavior using
• always block withedge event
• always _at_(posedge clock-signal)
• always _at_(negedge clock-signal)
• Nonblocking assignments (lt)
• _at_always(posedge clock-signal)
• begin
• output1 lt expression1
• . . .
• output2 lt expression2
• . . .
• end

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Simple Examples Flip-Flop, Register

• module flipflop(d, clk, q)
• input d
• input clk
• output q
• reg q
• always _at_(posedge clk)
• q lt d
• endmodule
• module flop3(clk, d, q)
• input clk
• input 30 d
• output 30 q
• reg 30 q
• always _at_(posedge clk)
• q lt d
• endmodule

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Simple Example Register with Reset

• Synchronous - resets on clock edge if reset1
• module flopr(clk, reset, d, q)
• input clk
• input reset
• input 30 d
• output 30 q
• reg 30 q
• always _at_(posedge clk)
• if (reset) q lt 4b0
• else q lt d
• endmodule

Q Whats wrong with async. Reset?
A Its susceptible to glitches!(use only for
system reset)
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Simple Example Register with Reset

• Asynchronous - resets immediately if reset1
• module flopr(clk, reset, d, q)
• input clk
• input reset
• input 30 d
• output 30 q
• reg 30 q
• always _at_(posedge clk or posedge reset)
• if (reset) q lt 4b0
• else q lt d
• endmodule

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Another Example Shift Register

• module shiftreg(clk, sin, q)
• input clk
• input sin
• output 30 q
• reg 30 q
• always _at_(posedge clk)
• begin
• q3 lt q2
• q2 lt q1
• q1 lt q0
• q0 lt sin
• end
• endmodule

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Shift Register Application

• module debounce (pb, clk_100Hz, pb_debounced)
• input pb
• input clk_100Hz
• output pb_debounced
• reg pb_debounced
• reg 30 shift_pb
• always _at_ (posedge clk_100Hz) begin
• shift_pb 30 lt shift_pb 20, pb
• if (shift_pb 4'b1111) pb_debounced lt 1
• else pb_debounced lt 0
• end
• endmodule // debounce

What does this circuit do? How does it work?
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Another Example 4-bit Counter

• Basic Circuit
• module counter(clk, Q)
• input clk
• output 30 Q
• reg 30 Q // Q assigned a value in always
• always _at_( posedge clk )
• begin
• Q lt Q 1
• end
• endmodule
• Questions How about carry?
• Putting carry in this code would register carry
• Result carry delayed one clock cycle
• Need to mix sequential combinational logic

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Combining Sequential and Combinational Outputs

• General circuit - both registered and comb.
  outputs
• Approach multiple always blocks

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Example Adding carry to 4-bit Counter

• module counter(clk, Q, carry)
• input clk
• output 30 Q
• output carry
• reg 30 Q // Q assigned a value in always
• assign carry (Q 4'b1111)
• always _at_( posedge clk )
• begin
• Q lt Q 1
• end
• endmodule

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Refining the Counter Synchronous Clear

• module counter(clk, clr, Q, carry)
• input clk, clr
• output 30 Q
• output carry
• reg 30 Q // Q assigned a value in always
• assign carry (Q 4'b1111)
• always _at_( posedge clk )
• begin
• if (clr) Q lt 4'd0
• else Q lt Q 1
• end
• endmodule

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Refining the Counter Asynchronous Clear

• module counter(clk, clr, Q, carry)
• input clk, clr
• output 30 Q
• output carry
• reg 30 Q // Q is assigned a value in always
• assign carry (Q 4'b1111)
• always _at_( posedge clr or posedge clk )
• begin
• if (clr) Q lt 4'd0
• else Q lt Q 1
• end
• endmodule

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Review BCD Counter

• How can it be parameterized?
• module bcdcounter(clk, reset, enb, Q, carry)
• input clk, reset, enb
• output 30 Q
• output carry
• reg 30 Q // a signal that is assigned a
  value
• assign carry (Q 9) enb
• always _at_( posedge clk )
• begin
• if (reset) Q lt 0
• else if (enb)
• begin
• if (carry) Q lt 0
• else Q lt Q 1
• end
• end

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State Machine Design

• Traditional Approach
• Create State Diagram
• Create State Transition Table
• Assign State Codes
• Write Excitation Equations Minimize
• HDL-Based State Machine Design
• Create State Diagram (optional)
• Write HDL description of state machine
• Synthesize

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Review - State Transition Diagrams

• "Bubbles" - states
• Arrows - transition edges labeled with condition
  expressions
• Example Car Alarm

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Review - State Transition Table

• Transition List - lists edges in STD
• PS Condition NS Output
• IDLE ARM' DOOR' IDLE 0
• IDLE ARMDOOR BEEP 0
• BEEP ARM WAIT 1
• BEEP ARM' IDLE 1
• WAIT ARM BEEP 0
• WAIT ARM' IDLE 0

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Coding FSMs in Verilog - Explicit Style

• Clocked always block - state register
• Combinational always block -
• next state logic
• output logic

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Coding FSMs in Verilog - Code Skeleton

• Part 1 - Declarations
• module fsm(inputs, outputs)
• input . . .
• input . . .
• reg . . .
• parameter NBITS-10
• S0 2'b00
• S1 2'b01
• S2 2b'10
• S3 2b'11
• reg NBITS-1 0 CURRENT_STATE
• reg NBITS-1 0 NEXT_STATE

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Coding FSMs in Verilog - Code Skeleton

• Part 2 - State Register, Logic Specification
• always _at_(posedge clk)
• begin
• CURRENT_STATE lt NEXT_STATE
• end
• always _at_(CURRENT_STATE or xin)
• begin
• case (CURRENT_STATE)
• S0 . . . determine NEXT_STATE, outputs
• S1 . . . determine NEXT_STATE, outputs
• end case
• end // always
• endmodule

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FSM Example - Car Alarm

• Part 1 - Declarations, State Register
• module car_alarm (arm, door, reset, clk, honk )
• input arm, door, reset, clk
• output honk
• reg honk
• parameter IDLE0,BEEP1,HWAIT2
• reg 10 current_state, next_state
• always _at_(posedge reset or posedge clk)
• if (reset) current_state lt IDLE
• else current_state lt next_state

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FSM Example - Car Alarm

• Part 2 - Logic Specification
• always _at_(current_state or arm or door)
• case (current_state)
• IDLE
• begin
• honk 0
• if (arm door) next_state BEEP
• else next_state IDLE
• end
• BEEP
• begin
• honk 1
• if (arm) next_state HWAIT
• else next_state IDLE
• end

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FSM Example - Car Alarm

• Part 3 - Logic Specification (contd)
• HWAIT
• begin
• honk 0
• if (arm) next_state BEEP
• else next_state IDLE
• end
• default
• begin
• honk 0
• next_state IDLE
• end
• endcase
• endmodule

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FSM Example - Verilog Handout

• Divide-by-Three Counter

reset
S0 out0
S1 out0
S1 out1
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Verilog Code - Divide by Three CounterPart 1

• module divideby3FSM(clk, reset, out)
• input clk
• input reset
• output out
• reg 10 state
• reg 10 nextstate
• parameter S0 2b00
• parameter S1 2b01
• parameter S2 2b10
• // State Register
• always _at_(posedge clk or posedge reset)
• if (reset) state lt S0
• else state lt nextstate

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Verilog Code - Divide by Three CounterPart 2

• // Next State Logic
• always _at_(state)
• case (state)
• S0 nextstate S1
• S1 nextstate S2
• S2 nextstate S0
• default nextstate S0
• endcase
• // Output Logic
• assign out (state S2)
• endmodule

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Example from VLSI 01 Recognizer

• Output 1 when input0 for 1 clock cycle, then 1

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Verilog Code - 01 Recognizer Part 1

• module recognizer (clk, reset, rin, rout)
• input clk, reset, rin
• output rout
• reg rout
• parameter 10 bit12'b00, bit22'b01
• reg 10 current_state, next_state
• always _at_(posedge clk)
• if (reset) current_state bit1
• else current_state lt next_state
• always _at_(current_state or rin)
• case (current_state)
• bit1
• begin
• rout 1'b0
• if (rin 0) next_state bit2

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Verilog Code - 01 Recognizer Part 1

• bit2
• begin
• if (rin 1'b0)
• begin
• rout 1'b0
• next_state bit2
• end
• else
• begin
• rout 1'b1
• next_state bit1
• end
• end
• default
• begin
• rout 1'b0
• next_state bit1
• end
• endcase

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Summary - Sequential Logic

• Build sequential logic using
• Clocked always for registered outputs
• Use non-blocking assignment lt
• Combinational always or assign for comb. outputs
• Use blocking assignment
• Dont use asynchronous reset
• Use parameters for state codes in FSMs

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Verilog Coding Guidelines - 1

• Use one file for each module.
• Include a header block in each file that
  includes
• Your names
• Brief description of module
• History
• Use template from ISE Edit menu
• Use comments liberally.
• Use meaningful signal names.
• Be consistent using capitalization and
  underscores.
• Properly indent your code, as shown in examples.

Dont use offensive signal names - (you dont
know who might read your code someday!)
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Verilog Coding Guidelines - 2

• Partition your design into leaf cells and
  non-leaf cells.
• Leaf cells contain assign statements or always
  blocks but do not instantiate other cells.
• Non-leaf cells instantiate other cells but
  contain no logic. (Minor exceptions OK to keep
  the code readable.) Define your combinational
  logic using assign statements when practical.
• Use only nonblocking (lt) assignments in always
  blocks that model sequential logic.
• Use only blocking () assignments in always
  blocks that model combinational logic.
• Avoid latch inferences in combinational always
  blocks!

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Verilog Coding Guidelines - 3

• Use only positive edge-triggered flip-flops for
  storage.
• Use parameters to define state names and
  constants.

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Lab 2 Goals

• Gain experience using Verilog for sequential
  logic
• Gain experience using parameterized modules
• Gain experience interfacing FPGA to I/O
• Design building blocks that will be useful later
• Design debug a complete sequential circuit
  (stopwatch)

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Lab 2 Overview

• 1. Parameterized counter (base on BCD example)
• BW parameter bitwidth
• M parameter counter modulus (counts from 0..M-1)
• Inputs clk, reset, enb
• Outputs Q, carry

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Lab 2 Overview (contd)

• 2. Write to divide 50 MHz clock down to 1000 Hz
• Use parameterized counter to divide by 25,000
• Use T flip-flop to give 50 duty cycle
• Use common clock for all flip-flops
• Dont use common reset with logic driven by
  divider

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Lab 2 Overview (contd)

• 3. Review debouncer discussed in class last time
• 4. Design a time-multiplexer circuit for
  7-segment display
• Inputs Four 4-bit BCD values, decimal points,
  slow clk
• Outputs segment enable, decimal point, 7-seg
  value

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Lab 2 Overview (contd)

• 5. Design a stopwatch accurate to 1/1000 sec.
• Buttons
• clear - resets time to 0.000 sec
• stop/start - alternately stops/starts count

stop/start
clear

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Coming Up

• More about event-driven simulation
• Verification and Testbenches