adaptive body bias for reducing process variations

1

• adaptive body bias for reducing process
  variations
• nuno alves
• 19 / october / 2006

2
background

• goal of processor design
• achieve maximum operating frequency
• meet power density constraint
• process variations create differences
• across a single die
• across multiple wafers and lots

3
differences in transistors ? so?

• some dies cannot be accepted because
• low frequency
• high power consumption

dies
4
solving leakage problem

• leakage can be controlled to some extent using
  body bias.
• remember non-zero body-to-source bias can
  modulate the threshold voltage of a transistors

5
reverse body bias (rbb)

• we can use rbb to reduce leakage power in standby
  mode by
• raising the voltage of the pMOS n-wells with
  respect to vdd
• or
• lowering the voltage of substrate relative to gnd

6
forward body bias (fbb)
use fbb to increase operating frequency in active
mode
the good
Vt ? by the lowering the source-body potential
barrier
the bad
increase in sub-threshold and substrate-to-source
leakage
lower Vt higher on current
slows down the discharge of nodes
hence higher performance
7
ideally

• Vt should be
• lowered for slow dies
• raised for leaky dies

accomplished by an adaptive body bias
8
testchip
21 subsites

• each subsite contains
• an abb generator
• control circuit

9
how it works? pt 1
slows things down
compare critical path with target clock period
the desired operating frequency is applied
externally
10
how it works? pt 2
output of first ff is sampled by second ff
this allows sufficient time for the body bias to
stabilize
11
how it works? pt 3
PD used to clock a counter
counter whose value represents the body bias to
apply
12
how it works? pt 4
converting digital code to an analogical
body voltage
13
how it works? pt 5

• the output voltage, which biases the the pMOS
  transistors is a function of
• VREF
• VCCA

output voltage
14
how it works? pt 6

• setting the bias by modifying
• VREF
• VCCA
• and
• setting a counter control bit

15
operation pt 1
initially frequency is lower than the target one
body voltage reduces, forward biasing the pMOS
transistor increasing frequency
16
operation pt 2
frequency has been matched
phase detector changes to a permanent 1
the counter is disabled, maintaining the body
voltage
17
operation pt 3
once optimal voltages are determined, they can be
programmed in the chip or supplies externally
18
simple adaptive body bias pt 1
optimum bias voltages are determined through
measurements

• example
• a microprocessor with many circuit blocks.
• find out the frequency of a critical path
• a central body bias determines the body bias to
  apply to achieve a desired frequency.
• apply this bias everywhere

2 total die area overhead
19
simple adaptive body bias pt 2
optimum bias is determined by applying a target
clock frequency
highest possible operating frequency for the
die under the given power constraint.
maximum clock frequency

• for this maximum frequency
• nMOS body bias is applied from outside
• pMOS body bias comes from on-chip control
  circuitry

20
simple adaptive body bias pt 3
pick target frequency
manually adjust nMOS body bias
repeat until we find the best combination of
lowest leakage with target frequency
pMOS body bias automatically adjusts
determine leakage power
21
effects of simple body bias pt1
NBB no body bias
22
effects of simple body bias pt2
conclusion 1

• when no body bias, only 50 dies are acceptable

mostly in the low frequency bin
23
effects of simple body bias pt3
conclusion 2

• frequency variation was reduced to 1 from 4.1
• more accepted dies (specially in the high
  frequency range)

24
effects of simple body bias pt4

• conclusion 3
• many dies fail to meet the leakage constraint
• due to the fact that a single circuit block is
  used to determine the body bias for all circuit
• and there are always intra-die variations.