Multilevel Ring Tuning for Post-Silicon Active Clock Deskewing

1
Multilevel Ring Tuning for Post-Silicon Active
Clock Deskewing

• Fariborz Dadnam
• Professor Lei He

2
PVT Variations

• Process Variations
• Inter-die
• Die-to-die variations
• Intra-die
• Within-die variations
• Significant impact on sub-micron technologies
• Voltage Variations
• Temperature Variations

3
Silicon Tuning

• Pre-Silicon

• Post-Silicon

• Design/layout phase
• Predictable variations

• After fabrication
• ATE feedback
• Adaptive circuits

Clock skew spatial variation Clock jitter
temporal variation
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Various PST Approaches

• Dynamically adjust clock skew
• Adjustable delay buffers (ADB) and Phase
  detectors (PD)
• Adjust the Vth of clock buffer transistors
• Hot carrier injection (HCI)
• Path-based learning
• Employing statistical timing tools to develop
  regression simulator

PST post-silicon tuning
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Different Techniques Objective

• Eliminating the number of PST components
• Area, power, cost
• Optimizing algorithms
• Accuracy, speed
• Organizing PST components
• Less components, optimization

6
Quadrantal Ring Tuning (QRT)An Active
Post-Silicon Tuning Method for Clock Deskewing
over PVT Variations
From the paper by J. G. Mueller and R. A. Saleh
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Delay-Locked Loop (DLL)
A single DLL unit
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Up/Down Detector (UDD)

• Measures the skew between the reference clock and
  the leaf (clk L and clk R)
• Concerns,
• Receiving accurate clock signals
• Setting up/down thresholds precisely

• In the locked state, no tuning adjustments will
  be made
• UP and DOWN can never both be high simultaneously

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Thermometer Code Generator and Tunable Buffer

• (TCG)

• (TB)

• Converts the control signals (UP/DOWN) from UDD
  to control word (e.g. 3-bit) for TB
• Placed next to TB
• Two clock-cycle wide
• One tuning step at a time

• Clock buffer/inverter to provide selectable delay
• Spans whole tuning range

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Stable DLL over PVT Variations

• Distribution across entire chip ? subject to
  various intra-die PVT variations
• Step size (ss)
• Skew threshold (Sth)

ss tuning_range/(bits - 1) Sth 1.5 ss

• To ensure,
• DLL locking
• Loop stability

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QRT Architecture

• Tuning Zones Selection
• Simpler control of fewer, large tuning zones
• vs.
• Higher precision/accuracy of more, small tuning
  zones
• UDDs Location
• Minimize routing
• and
• Maximize skew measurement accuracy

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Single-Level QRT
Feedback (or tuned) clock of one zone becomes the
reference clock of its counter-clockwise
neighboring zone!
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Multi-Level QRT

• Total of sixteen additional UDDs, TCGs, and TBs
• Tuning range of 50ps for clock level-2 vs. 20ps
  for clock level-3
• The sub-skews within each quadrant will be
  reduced, and therefore, the overall chips clock
  skew will also be reduced

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PVT Variation Modeling

• PVT Variations
• Spatial variations (cone function)
• z2 (x a)2 (y b)2 in MATLAB
• z(x, y) cone function
• Random variations (Monte Carlo simulation)
• gauss() function in HSPICE
• Gaussian RV(µ, s)

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Simulation Variables

• Transistors
• Channel width
• Leakage
• Capacitors
• Resistors
• Wires
• Length
• Resistance per unit length
• Capacitance per unit length

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Total PVT Variation

• P Pnom ?Pinter ?Pspatial(xi, yi)
  ?Prandom,i
• Pnom nominal value
• ?Pinter inter-die variation
• ?Pspatial intra-die variation, function of
  location (x, y)
• ?Prandom some amount of random variation

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Result Single Level
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Result PVT Variations
(A)
(B)
(C)
(D)
(E)
(F)
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Result Overall Comparison
No tuning
QRT level-2 only
QRT level-2 3
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References

• 1 X. Li, B. Taylor, Y. Chien and L. T.
  Pileggi, "Adaptive Post-Silicon Tuning for Analog
  Circuits Concept, Analysis and Optimization,"
  IEEE, pp. 450-457, 2007.
• 2 Z. Lak and N. Nicolici, "A New Algorithm for
  Post-Silicon Clock Measurement and Tuning," IEEE,
  pp. 53-59, 2011.
• 3 J. G. Mueller and R. A. Saleh, "Autonomous,
  Multilevel Ring Tuning Scheme for Post-Silicon
  Active Clock Deskewing Over Intra-Die
  Variations," IEEE, vol. 9, no. 6, pp. 973-986,
  June 2011.
• 4 S. H. Kulkarni, D. Sylvester and D. Blaauw,
  "A Statistical Framework for Post-Silicon Tuning
  through Body Bias Clustering," ICCAD, pp. 39-46,
  November 2006.
• 5 J.-L. Tsai, L. Zhang and C. C.-P. Chen,
  "Statistical Timing Analysis Driven
  Post-Silicon-Tunable Clock-Tree Synthesis," IEEE,
  pp. 574-580, 2005.
• 6 J. G. Mueller and R. Saleh, "A Tunable Clock
  Buffer for Intra-die PVT Compensation in
  Single-Edge Clock (SEC) Distribution Networks,"
  IEEE, pp. 572-577, 2088.
• 7 S. Naffziger, B. Stackhouse, T. Grutkowski,
  D. Josephson, J. Desai, E. Alon and M. Horowitz,
  "The Implementation of a 2-Core, Multi-Threaded
  Itanium Family Processor," IEEE, vol. 41, no. 1,
  pp. 197-209, January 2006.
• 8 Y. Pu, X. Zhang, K. Ikeuchi, A. Muramatsu,
  A. Kawasumi, M. Takamiya, M. Nomura, H. Shinohara
  and T. Sakurai, "Post-Silicon Clock Deskew
  Employing Hot-Carrier Injection Trimming With
  On-Chip Skew Monitoring and Auto-Stressing Scheme
  for Sub/Near Threshold Digital Circuits," IEEE,
  pp. 294-298, 2011.
• 9 M. Y. Kao, K.-T. Tsai and S.-C. Chang, "A
  Robust Architecture for Post-Silicon Skew
  Tuning," IEEE, pp. 774-778, 2011.