VariationTolerant Circuit Design Techniques

1
Variation-Tolerant Circuit Design Techniques

• Tanay Karnik
• Circuits Research Lab, Intel Corporation
• Acknowledgements
• Vivek De, Jim Tschanz, Jianping Xu, Ram
  Krishnamurthy, Steven Hsu, Keith Bowman, Ali
  Keshavarzi, Muhammad Khellah, Nam Sung Kim, Siva
  Narendra, Peter Hazucha, Gerhard Schrom, Fabrice
  Paillet, Noel Menezes, Shekhar Borkar, Intel
  Corporation
• Prof. David Blaauw, University of Michigan
• Prof. Kaushik Roy, Purdue University
• Dr. Michael Nicholaidis, TIMA, France

2
Outline

• Motivation
• Static techniques
• Dynamic techniques
• adaptive circuits
• error recovery
• regulator integration
• Summary

3
Transistor Research
4
Intel Mobile Products
Single Core Processors
Dothan (90nm)
Banias (130nm)
Dual Core Processors
Yonah (90nm)
Penryn (45nm)
Merom (65nm)
Source www.Chip-Architect.com
5
Technology Trends

• Continue Moores Law
• /transistor scaling
• Energy/operation scaling
• More transistors per chip
• Deliver higher performance systems
• Power is the limiter
• Larger delay and power variability

6
Technology Outlook
7
Sources of Variability
8
P, V, T Variations
Voltage
Process

• Die-to-die variation
• Within-die variation
• Static for each die

• Chip activity change
• Current deliveryRLC
• Dynamic ns to 10-100us
• Within-die variation

Very slow
Device Ion
Temperature
Years

• Activity ambient change
• Dynamic 100-1000us
• Within-die variation

Time dependent Degradation Aging NBTI
9
Cost of Variations

• Underestimating Variations
• Functional yield loss
• Performance reduction
• Increases silicon debug time
• Increases manufacturing effort

• Overestimating Variations
• Increases design time
• Larger die size
• Rejection of otherwise good design options
• Missed market windows
• Increases design effort

10
Static Techniques
11
Layout Restrictions - Orientation
12
Layout Restrictions - Quantization
Vdd
Vdd
Op
Ip
Op
Vss
Vss
13
Layout Restrictions - Routing
14
Static variation compensation

• Measure
• Processor frequency, power
• Variation sensors, ring oscillators
• Adapt
• Clock distribution delays
• On-die body bias
• Supply voltage

15
Adaptive Body Bias Process Variations
180nm ABB testchip

• WID-ABB
• 20X lower Fmax variation
• 97 high-bin parts

• ABB
• 6X lower Fmax variation
• 30 high-bin parts

16
Effectiveness of Adaptive Biasing
17
Input offset compensation circuit
 

• Active input offset compensation circuit
• - simple structure
• - programmable output voltage with 8-bit high
  resolutio
• Voltage offset range -200 mV to 200 mV
• Voltage offset resolution / 1 bit 1.56 mV

 
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Input Offset Cancellation
offset control
Vi
Vo
-

Vi-
Vo-
Vout
Vout
Vclk
Vin-
Vin
Vin
Vin-
Vbias
Vbias

• delay matching required
• Fswitching gt 2 Finput

• clocked compensation
• enables high speed operation

• simple structure
• programmable 8-bit high resolution

19
Time Borrowing Flip-Flops
TB Flip-Flop

• Insertion of clock path inverters provides a
  transparency window (TW)
• Connections to master-latch pass gate and
  tri-state inverter change for an odd number of TW
  inverters
• Clocking energy overhead for larger TW

K. Bowman et. al., ISLPED 2006
20
TB Flip-Flops - N-Cycle Interconnect
TB N-Cycle Interconnect

• Transparency windows enable
• Amortization of clock skew jitter
• Averaging of WID data delay variations
• Min-delay constraints for interconnects are less
  stringent than logic
• TW can be relatively large fraction of cycle time

K. Bowman et. al., ISLPED 2006
21
TB Flip-Flops Active Energy

• Active Energy FMAX trade-off quantified by
  sweeping tW in model
• FMAX gains saturate as data delay averaging
  approaches ideality
• Mean FMAX gain of 3.5 at equal active energy

K. Bowman et. al., ISLPED 2006
22
TB Flip-Flops Average Energy

• TB interconnects enable 4-6 mean FMAX gain and
  10 average energy savings

K. Bowman et. al., ISLPED 2006
23
TB Flip-Flops FMAX Gain
65nm Variations Increase WID Delay Variance by 2X
65nm Variations

• Maximum mean FMAX benefit ranges from 4-7.5 for
  65nm process
• For 2X larger WID delay variance (1.41X larger
  standard deviation), maximum mean FMAX gain rises
  to 5-10

K. Bowman et. al., ISLPED 2006
24
Dynamic Variation Compensation
25
Dynamic adaptive design

• Dynamic variations voltage, temperature, aging
• Guardbanding performance or power penalty
• Optimally sense and respond to environment

Adapt Body bias (NMOS PMOS) FBB Increase F
and ISB RBB Reduce F and ISB Supply voltage
Off-chip voltage regulator Frequency DLL for
fine-grain F changeSwitch between multiple PLLs
Sense Temperature on-die thermal
sensors Voltage droop (1st, 2nd, 3rd) on-die
droop detectors Processor workload off-chip
current sensoractivity monitorssoftware hooks
26
Itanium Power Controller
Montecito90-nm Itanium processor
S. Naffziger et. al., The implementation of a
2-core multi-threaded Itanium-Family Processor,
ISSCC 2005
27
Itanium Power Controller
Reduced power variation!
S. Naffziger et. al., ISSCC 2005
28
Itanium Power Controller
Voltage
Transition to Low Power Draw
Power
Transition to High Power Draw
Current
Transition is fast enough that thermal budget is
maintained
R. McGowen, Power and temperature control on a
90nm Itanium family processor, ISSCC, 2005
29
Dynamic Adaptive TCP/IP Processor
90nm CMOS 964K transistors 1.3W _at_ 3GHz
J. Tschanz et. al, Adaptive frequency and
biasing techniques for tolerance to dynamic
temperature-voltage variations and aging, ISSCC
2007.
30
Frequency Change Algorithms
Frequency
J. Tschanz et. al., ISSCC 2007
31
Dynamic Droop Response
32 frequency increase
23 average frequency improvement
J. Tschanz et. al, ISSCC 2007.
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Dynamic Response
Adaptive
2943 MHz
2598 MHz
Fixed frequency
12 frequency gain at same power
Die Temperature
1.4 avg frequency gain
Frequency
NMOS body bias
J. Tschanz et. al, ISSCC 2007.
33
Aging Compensation with Body Bias
3 Fmax improvement at 0.9V
PMOS body bias for compensation
J. Tschanz et. al, ISSCC 2007.
34
On-Die Leakage Sensor For Measuring Process
Variation

• High leakage sensing gain 90nm dual-Vt,
  Vdd1.2V, 7 level resolution, 0.66 mW _at_80Cº

C. Kim et al. , VLSI Circuits Symp. 04. Source
Kaushik Roy, Purdue University
35
Path-level Delay Fault Detection
Correct operation
Data sampling errordue to voltage droop

• Challenges
• Detection and propagation of fault
• Metastability
• Error correction scheme

36
Shadow Latches for Error Detection

• TIMA, France
• IROC Technologies
• http//www.iroctech.com
• Developed for soft error tolerance
• Tools to estimate FIT rates
• Tools to harden netlists

Source Michael Nicholaidis, TIMA, France,
VTS1999, DATE2000.
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Razor I Error Detection Recovery

• Goal reduce voltage margins with in-situ
  error detection and correction for delay failures
• Augment flip-flops on critical path with a
  shadow latch - samples off the
• negative clock edge or a delayed clock

clk
Q
D
0
Main Flip-Flop
Local Meta Detector
1
Error
Comparator
RAZOR FF
Restore

• Upon failure Overwrite main flip-flop with
  correct data from the shadow latch
• Ensure that the shadow latch is always correct by
  conventional design
• Razor I developed in collaboration with Austin
  and Mudge

Source David Blaauw, University of Michigan.
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Razor Flip-Flop Circuit Schematic
Master
Slave
Clk
nClk
Restore
Q
D_in
G1
nClk
Clk
nClk
Clk
Error
Source David Blaauw, University of Michigan.
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Razor Self-tuning Microprocessor
140MHz
120MHz
Percentage Error Rate
Normalized Energy
ARM processor with Razor Technology
0.18um Transistors 1.6M Power overhead 2.9
Error Rate
Energy
Error detection
Voltage (in Volts)
Point of First Failure
20 energy reduction at same frequency Error
rate must be small (ltlt1)
S. Das et. al, A self-tuning DVT processor using
delay-error detection and correction, VLSI 2005.
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Distribution of Net Energy Savings
140MHz
120MHz
Number of Chips
Number of Chips
Percentage Savings
Percentage Savings
Distribution of Net Energy Savings Over Worst
Case for 33 measured chips
Source David Blaauw, University of Michigan.
41
Self-Regulating Voltage using Error Detection

• Razor voltage regulation
• Tune processor voltage based on error rate
• Eliminate safety margins, purposely run below
  critical voltage
• Data-dependent latency margins
• Trade-off voltage power savings vs. overhead of
  correction

Pipeline IPC
Total Energy
Processor Energy
Processor Energy w/ overhead
Supply Voltage
Optimal Voltage

• Analogous to wireless power modulation

Source David Blaauw, University of Michigan.
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Razor Voltage Controller
Vdd
Voltage Regulator
FPGA
reset
12 bit DAC
DC-DC
Voltage Control Function
Esample
Ediff
CPU
Error Count
Eref
Ediff Eref - Esample
Razor Voltage Control Loop
Controller Output Voltage(V)
Percentage Error Rate
Time (Seconds)
b) Run-Time Response of the Voltage Controller at
750KHz Error Sampling Frequency
Source David Blaauw, University of Michigan.
43
Low-Energy Error Detection Sequentials
Source Keith Bowman, et al., ISSCC 2008.
44
Low-Energy Error Detection Sequentials
Source Keith Bowman, et al., ISSCC 2008.
45
Low-Energy Error Detection Sequentials

• Timing-error detection and recovery
  demonstration.
• Data from input buffer arrives late at 3rd
  pipeline stage
• (a) Detect error
• (b) Invalidate output data
• (c) Halve FCLK
• (d) Replay instruction
• (e) Validate output data
• (f) Resume target FCLK
• Avg path FCLK gains from eliminating V T
  guardbands
• Path FCLK gains are measured by comparing EDS at
  nominal conditions to the conventional design at
  worst-case conditions

Source Keith Bowman, et al., ISSCC 2008
46
Low-Energy Error Detection Sequentials

• Measured throughput (TP) and error rate versus
  clock frequency (FCLK)
• Measured maximum throughput (TP) for resilient
  and conventional designs versus supply voltage

Source Keith Bowman, et al., ISSCC 2008.
47
Power Supply Industry Trends

• USD 28 Billion industry
• 1000 manufacturers of ACDC and DCDC
• a reactive industry, non-marketable for OEMs
• Easy to enter, difficult to grow
• growth ACDC 4.6, DCDC 3
• 15 RD ? 50 profit to sustain
• 5 (1 Billion) RD spending
• Efficiency
• utility bills for server farms
• Power management and digital power

Source Mohan Mankikar
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Microprocessor Platforms
Desktop
Server
platform powerdelivery
Handheld
Mobile

• area intensive decaps - platform area saving
  potential

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Integrated-Converter Benefits

• 41 conversion reduces current to 0.29x, off-chip
  decoupling to 0.15x, and I2R loss to 0.09x
• Separate memory supply can avoid Vccmin problems

Gerhard Schrom, et al., ISLPED 2004.
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25A/mm2 Linear Regulator for 2-VCC

• 90nm communication process
• lt10PP droop with 100 load change
• 0.54ns response time

Peter Hazucha, et al., VLSI Circuits Symposium
2004.
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DC-DC Converter Test Chip
Peter Hazucha, et al., VLSI Circuits Symposium
2004.
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DCDC Switching Converter
VIN1.4V, VOUT1.1V
VIN1.2V, VOUT0.9V

• Roll-off at high current due to series R
• Efficiency improves at 1.4V due to lower MOSFET
  resistance, peaks at 87.7

Peter Hazucha, et al., VLSI Circuits Symposium
2004.
53
Supply Resonance Suppression
Impedance peaks at 140 MHz
Jianping Xu, et al., ISSCC2007
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Band-Limited Active Damping
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Band-Limited Active Damping

• 77 resonance suppression 12.76dB
• Obtained suppression current density of 8.5 A/mm2
• RSC cell occupies 0.001 mm2
• less than 1 area overhead and 3 power overhead

Jianping Xu, et al., ISSCC2007
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Memory Circuits

• Register Files
• Split wordline
• PVT compensated keeper
• mask, trim, tune
• NAND instead of stacked PMOS
• SRAM / cache
• Selective sleep for retention or collapse
• Voltage modulation
• bit-line pulsing
• word-line pulsing
• word-line overdrive/ underdrive
• cell voltage underdrive / collapse
• Data sensing
• sense-amplifier sharing
• optimized timing
• Variation tolerance
• self-repair with leakage monitors and tunable VBB
• active sleep, active voltage modulation
• tunable timing and trimming

Tanay Karnik, et al., ICCAD2007
57
Summary

• Must do
• Continue Moores Law
• /transistor scaling
• Energy/operation scaling
• More transistors per chip
• Deliver higher performance systems
• Solutions
• Static and dynamic variation tolerant circuits
• Memory/RF scaling circuits

58
References

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• A 4.2GHz 0.3mm2 256kb Dual-V/sub cc/ SRAM
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