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Alberto Annovi

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Two smaller FTKs in cascade (a` la CDF): 8 SCT layers fitted first, then 3 ... CDF. XFT in COT. SVX. Studying different architectures: optimize AM use ... – PowerPoint PPT presentation

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Title: Alberto Annovi


1
Fast Tracker
A hardware track finder for the ATLAS trigger.
  • Alberto Annovi
  • for the Fast Tracker collaboration
  • Istituto Nazionale di Fisica Nucleare
  • Laboratori Nazionali di Frascati

11th ICATPP Conference on Astroparticle,
Particle, Space Physics, Detectors and Medical
Physics Applications
2
Outline
  • The Fast Tracker for ATLAS level 2
  • Physics motivations
  • Fast Tracker internals
  • Fast Tracker performances
  • A pixel clustering algorithm for FTK

3
TRIGGER _at_ HADRON COLLIDERS
Hard Life!
109
107
105
Events/s with L 1034 cm-2s-1
103
s
10
B0-gtK?
10-1
10-3
4

30 minimum bias events H-gtZZ-gt4m
Where is the Higgs?
m
m
Help!
m
m
Tracks with Ptgt2 GeV
5
Builds on the Silicon Vertex Trigger experience
Fast Track (FTK)
LHC
For SVT see G. Punzi plenary talk (Monday)
6
Fast tracking in pixel and SCT det.
Total of readout channels PIXELS 80
millions SCT 6 millions
7
CALO MUON TRACKER
PIPELINE
LVL1
ROD
FE
FE
Buffer Memory
Buffer Memory
Raw data ROBs
Fast network connection
CPU FARM (LVL2 Algorithms)
8
FTK collaboration schedule
Argonne National Lab J. Proudfoot and J.
Zhang Univ. of Chicago A. Boveia, E. Brubaker,
F. Canelli, M. Dunford, A. Kapliy, Y.K. Kim, C.
Melachrinos, M. Shochet, and J. Tuggle Univ. and
INFN Ferrara L. Tripiccione INFN Frascati A.
Annovi, M. Beretta, and P. Laurelli Univ. of
Illinois at Urbana-Champaign H. DeBerg, A.
McCarn, M. Neubauer, and S. Wolin Harvard Univ.
M. Franklin, C. Mills, and M. Morii Univ. and
INFN of Pisa E. Bossini, V. Cavasinni, F.
Crescioli, M. DellOrso, P. Giannetti, M.
Piendibene, G. Punzi, F. Sarri, I. Vivarelli, G.
Volpi, and L. Sartori Waseda University N.
Kimura and K. Yorita
  • RD Proposal to work on TDR approved Feb 2008
  • Preparing the TDR (2009) to be approved 2010 for
    SLHC Phase I
  • Expected inst. luminosity 1034 31034 (and
    1035 later on)
  • staging is being considered to take data with
    FTK also before the Phase I shutdown 
  • it is very important to learn at lower
    luminosities before going up to SLHC 
  • early impact on physics lepton isolation,
     b-tagging and tau-tagging studies
  • (Z?bb  Z?tau tau)

9
Physics motivations
B-tagging FTK vs offline
10
Z0 ? bbbar for b-jet calibration
  • Measuring the Z0 ? bbbar for
  • b-jet calibration
  • improve top mass resolution
  • bbbar resonances (e.g. Higgs)

11
Higher efficiency for bbH/A ? 4 b-jets
4-Jet Trigger Rate _at_2x1033
Careful study of the 4-jet L1 trigger cross
sections
w/ FTK
(not 90 effic. for true Pt)
w/o FTK
w/o FTK assumes that level-2 execution time
limits level-1 jet rate to a few hundred Hz.,
e.g. only jet threshold sharpening at level 2
no b-tagging.
12
Higher efficiency for bbH/A ? 4 b-jets
  • At lower mass, the signal is badly sculpted by
    the non-FTK jet threshold
  • Larger discovery region with FTK

Signal dijet mass distribution at the trigger
13
e/m isolation _at_ high luminosity
Calorimetric isolation suffers from high event
multiplicity! Isolation with tracks has little
sensitivity to pile-up events ?it becomes easy
with FTK
Lepton identification primary vertices fast
identification ? Isolation with tracks of
PtgtThreshold and from right vertex
14
  • Find low resolution track candidates called
    roads. Solve most of the combinatorial problem.

Pattern recognition w/ Associative Memory
IEEE Trans. On Nucl. Sci., vol. 53, pp. 2428-2433
(2006)
http//www.pi.infn.it/7Eorso/ftk/IEEECNF2007_2115
.pdf
Excellent results with linear approximation!
15
Pattern matching
The Pattern Bank
...
Associative Memory (AM) see L. Sartori talk
Tuesday
16
Divide into f sectors
ATLAS Pixels SCT
1/2 f AM
Allow a small overlap for full efficiency
1/2 f AM
6 buses 40MHz/bus (to be increased)
11 Logical Layers full h coverage
  • 8 f regions each with
  • 6 sub-regions (h-f towers)
  • df25o, dh1.7
  • bandwidth for up to
  • 310E34 cm-2s-1

17
Pixels SCT
cluster finding split by layer
RODs
overlap regions
HITS
Data Formatter (DF)
6x h-f towers
50100 KHz event rate

S-links
Remove duplicate trks
Offline quality Track parameters
Track data ROB
Raw data ROBs
18
The pattern bank for pattern matching
90
Pattern bank size strongly depends on superstrip
size. It is a compromise between coarser
superstrips fewer patterns but many more fits
88
Single muon efficiency
Bank size (M patterns/region)
4M patterns/region use current AMchip
50M patterns/region with future AMchip
gt100M patterns/region with AMchip tree search
processor (TSP)
19
Studying different architectures optimize AM
useRedundancy for high luminosity
  • Two smaller FTKs in cascade (a la CDF) 8 SCT
    layers fitted first, then 3 pixels layer SCT
    fitted segment
  • Two Half-SS shifted banks used in parallel to
    improve SS resolution
  • New algorithm inserted between the AM and the TF
    The Tree Search Processor (TSP) - NIM A287 (1990)
    436-438
  • http//www.pi.infn.it/paola/Tree_search_a
    lgorithm.pdf

Shown today
20
Binary search to go down to better SS resolutions
FAT ROAD Found by AM (default SS for example or
even larger)
PARENT PATTERN
Depth 0
Depth 1
PATTERN BLOCK
Depth 2
THIN ROAD
  • Advantages
  • pattern bank saved in dense RAMs
  • high degree of parallelism

Algorithm NIM A287 (1990) 436-438
http//www.pi.infn.it/paola/Tree_search_algorith
m.pdf Tree Search Processor NIM A 287, 431
(1990), http//www.pi.infn.it/orso/ftk/NIMA287_4
31.pdf IEEE Toronto, Canada, November 8-14 1998
http//www.pi.infn.it/paola/TSP_v14.pdf
21
How much workload for the GF?
Full simulation WH events _at_1034 cm-1 s-1
GF upgrade for SVT 1 fit/ns with a Xilinx Virtex
5 FPGA (XC5VSX95T)
AMchip 3.8M patterns/region TSP 108M
patterns/region
ltfits/eventgt 200k Barrel only Region 0
http//www.pi.infn.it/7Eorso/ftk/IEEECNF2007_2115
.pdf
Doable with a few FPGAs/region
Million of fits
22
A hardware architecture able to digest WH ?
lnubb 1034 pileup _at_ 75kHz event rate
1 FTK f-region 6 h-f towers
h-f Tower 0
h-f Tower 5
6500 ltRoadsgt/ev ? 3600 for RW reduction ?
600/ev if divided in 6 engines ? 600 75 kHz
45 MHz ?1 Road each 22 ns
....
SUPER Bins
SUPER Bins
ROADS
ROADS
HITs
DO TF
12 L
12 L
HITs
DO TF
TRACKS
TRACKS
400 k ltFitsgt/ev. ? 66 k ltFitsgt/ev. in 6 engines ?
66 k 75 kHz ? 5 Gltfitsgt/s ? 5 fit/ns
TRACKS MERGING HW
Tracks to Level 2
1000 hit/ev/layer corrected for overlaps between
region ? 1000/3330/ev. Dividing in 6 h-f towers
(with 100 contingency for tower overlap) ? 330
75 kHz 25 MHz OK even for current AMchip!
23
8x core crate layout (TSP option)
All found tracks
  • 12 AM boards
  • Today technology
  • 3.8 106 Patterns today Amchip
  • 100M patterns TSP
  • For 2014(?) installation
  • O(50 106 ) Patterns for 90 nm
  • ? ??Giga patterns future TSP

CPU vme
Hit Warrior
CUSTOM BACKPLANE
1 h-f tower
FTK Output tracks
FTK INPUT
24
Tracking quality on single muon events
  • We compare FTK-reconstructed tracks with an
    offline algorithm (IPAT)
  • Resolutions are wrt all truth tracks with pt gt 1
    GeV and ? lt 2.5
  • Performances are comparable

25
sFTK soffline?30µm
FTK proposal no pile-up barrel only space
points
November 2008 nopile-up full h coverage raw
hits
WH 1034 pile-up
Single muons
0 2 4 6 8 10 12 14
16
PT GeV
26
t-jet efficiency rejection Single Prong (1,0)
? lt 0.8 for jet 1033 Lumi
Efficiency vs. ?
Efficiency vs. pT
Fakes as a function of jet Pt
? end
Fakes as a function of jet ?
27
SVT Online beamline fit correction
L. Ristori et al.
Nucl.Instrum.Meth.A518532-536,2004
  • Raw

ltdgt Ybeamcosf Xbeamsinf
http//www-cdf.fnal.gov/cdfnotes/cdf7208_bw_online
.ps
Subtracted
Also used to monitor beam profile. Useful
information for accelerator people!
? end
28
Pixel clustering for the Fast TracKer
  • Pixel clustering device for the ATLAS FastTracKer
    processor
  • 1st application design motivation
  • http//twiki.cern.ch/twiki/bin/view/Atlas/FastTrac
    ker
  • Main challenge input rate 160Gibts
  • 132 S-link fibers from all pixel RODs
  • Running at 1.2 Gbits (total 160Gbits)
  • 32bit words at 40MHz, 1 hit/word
  • Use hits at 40MHz as benchmark
  • Focus on clustering quality for level-2
  • Illustrate a general clustering strategy

FTK reconstructs tracks for level 2
29
The problem
  • Clustering is a 2D problem
  • Associate hits from same cluster
  • Loop over hit list
  • Time increases with occoupancy instantneous
    luminosty
  • Non linear execution time
  • Calculate cluster properties
  • e.g. center, size, shape
  • Goal execution time linear with number of hits
  • Not a limiting factor even at highest inst.
    Luminosity

Loop over list of hits
6
7
1
2
3
4
5
8
9
10
30
The algorithm working principle
Core logic Hit associated into clusters
FPGA replica of pixel matrix
Load all module hits
select left most top most hit
Loop over clusters in a module
propagate selection through cluster
Loop over events and pixel modules
Eta direction --gt
Pixel module is a 328x144 matrix. Replicate it in
a hardware matrix. The matrix identifies hits in
the same cluster (local connections).
read out cluster
2nd pipeline stage
Average calculator
out
high level cluster analysis
? end
31
Clustering by 328x8 slices?
Shift of hits comes for free (no extra time)!
Just use the slice as a circular buffer in the
eta direction. Then hits are shifted by
redefining the first column.
SLIDING WINDOW with one xc5vlx155 process one
S-Link Implement 2 processing matrixes. Process
hits at 40MHz rate.
32
Two priority logic chains
hit
Control logic
hit
sel
select
hit
hit
pixel cell
sel
hit
  • a 1st priority logic
  • needed to select first hit
  • a 2nd priority logic
  • needed to readout selected hits (cluster)
  • position from address bus

select
hit
pixel cell
select
This logic selects the top most pixel. Similar
logic to select the left most column with a hit.
X 328 pixels in a column and 144 columns
33
The elementary cell
Cluster definition Contiguous hits along side
or corner Flexibility to redefine it
3 STATES (2 FLIP-FLOPS) IS_EMPTY IS_HIT IS_SELECT
ED
SEL HIT
Combinatorial logic
IS_HIT
1st neighborhood IS_SELECTED
8
SEL FOR READOUT
IS_SELECTED
WRITE
ROW SEL
AND
9
COLUMN SEL
Row addr Bus (output)
34
Conclusions
  • FTK performs global track reconstruction at
    Level-1 trigger rate
  • Using massively parallel Associative Memories,
    FTK will provide a complete list of 3D tracks at
    the beginning of Level-2 processing
  • Time saved by FTK can be used in Level-2 for more
    advanced algorithms
  • Bonus access to tracks outside Regions of
    Interest
  • FTK easily integrates with current ATLAS DAQ
  • Builds on success of Silicon Vertex Trigger (SVT)
    at CDF
  • More info http//www.pi.infn.it/orso/ftk/
  • https//twiki.cern.ch/twiki/bin/view/Atlas/FastTra
    cker

35
Thanks for your attention
36
From non-linear to linear constraints
Non-linear geometrical constraint for a circle
F(x1 , x2 , x3 , ) 0
But for sufficiently small displacements
F(x1 , x2 , x3 , ) a0 a1Dx1 a2Dx2 a3Dx3
0
with constant ai
(first order expansion of F)
37
Constraint surface
14 measured coordinates x1 x14 5 parameters to
fit f, d0, pT, h, z0 9 constraints
Linear approximation is good within any given set
of physical modules.
38
  • Discovery reach (FTK double b-tag ? 25 Hz L2
    output)
  • Note that FTK is rather insensitive to a much
    higher background rate due to either higher
    luminosity or MC ? reality.
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