VHDL Structures and Syntax

1
VHDL Structures and Syntax
2
Identifiers and signals

• Identifier (naming) rules
• Can consist of alphabet characters, numbers, and
  underscore
• First character must be a letter (alphabet)
• Last character cannot be an underscore
• Two underscores in a row are not allowed
• Upper and lower case are equivalent (case
  insensitive)
• VHDL keywords cannot be used as identifiers
•  
• Signals represent wires or outputs of gates, FFs,
  etc.
• Ports (ins, outs, inouts) in the entity are
  signals
• Internal signals are often needed in complex
  models and are declared in the architecture
  description as follows

3
Signals

• architecture architecture_name of entity_name is
• signal signal_name type
• signal signal_name type
• begin
• end architecture architecture_name
•  
• The signal type can be bit, bit_vector,
  std_logic, std_logic_vector

4
Signals

• Signals can be initialized to a beginning value
  at the declaration BUT this is meaningless to
  synthesis tools since no hardware mechanism
  exists to produce this power-up init value
• Example
• Signal count bit_vector(3 downto 0) 0101
• Here is used to indicate an initial immediate
  assignment
• But the normal assignment operator is lt
• Example
• Count lt 0101
• This does correspond to synthesizable logic and
  will be recognized by synthesis tools

5
Attributes

• Attributes provide information about items such
  as signals
• The most important signal attribute is event
  which yields a Boolean value of true if an event
  has just occurred on the signal to which the
  attribute is applied
• An event on a signal means a change in value
• Another useful attribute is range which is used
  as
• for i in arange loop
• a lt (others gt 0)
• end loop

6
Attributes

• Example 
• entity DFF is
• port (CK, D in bit
• Q out bit)
• end entity DFF
• architecture UKBB of DFF is
• begin
• process (CK)
• if (CKevent AND CK1) then
• Q lt D -- occurs only in the rising edge of
  CK
• end if
• end process
• end architecture UKBB

7
Logic operators

• Logic operators are the heart of logic equations
  and include
• AND OR NOT
• NAND NOR
• XOR XNOR
• There is NO order of precedence so use lots of
  parentheses

8
Errors

• entity many_errors is port
• a bitvector (3 to 0)
• b out std_logic_vector (0 to 3)
• c in bit_vector (5 downto 0))
• end many_errors
• architecture arch_error of many_error
• begin
• label process
• begin
• if c xF then
• b lt a
• else
• b lt 0101
• end if
• end label
• end arch_error

9
Unintentinal memory

• label process (a,b)
• begin
• if a b then
• rst lt 1
• end process
• label process (a,b)
• begin
• rst lt 0
• if a b then
• rst lt 1
• end if
• end process