VHDL Structures and Syntax

1
VHDL Structures and Syntax
2
VHDL for synthesis

• architecture ninja of foo is
• begin
• p1 process (s)
• begin
• if s 00 or s 11 then
• y lt 1
• else
• y lt -
• end if
• end process
• end ninja

3
VHDL for simulation

• function resolved (a,b std_ulogic) return
  std_ulogic is
• begin
• if a / b then return (X)
• else return (a)
• end
• p1 process (a,b,c)
• begin
• x lt a and b and c after 5 ns
• end process
• whatever can be synthesized, can be simulated
• whatever can be simulated may not be
  synthesizable

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std data types

• type std_ulogic is ( U, -- uninitialized
• X, -- forcing unknown
• 0, -- forcing 0
• 1, -- forcing 1
• Z, -- high impedance
• W, -- weak X
• L, -- weak 0
• H, -- weak 1
• -, -- dont care
• )
• subtype std_logic is resolved std_ulogic --
  (std_logic_1164 package)
• U, X and W are not supported by synthesis
  tools

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Event-driven simulation
x a.b.c
5ns
a
b
c
x
d
d
(0, 5 ns) (1, 5ns d)
x
6
Event-driven simulation
x abc
10ns
5ns
a
b
c
x
d
d
(0, 10ns d)
x
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Signals and variables

• architecture yummy of and8 is
• begin
• p1 process (a_bus)
• variable tmp bit 0
• begin
• tmp 1
• for i in 7 downto 0 loop
• tmp a_bus(i) and tmp
• end loop
• x lt tmp
• end process
• end yummy

• architecture yikes of and8 is
• signal x bit 0
• begin
• p1 process (a_bus)
• begin
• x lt 1
• for i in 7 downto 0 loop
• x lt a_bus(i) and x
• end loop
• end process
• end yikes

8
Some more data objects

• constant
• constant width integer 8
• package, entity, architecture, process
• signal
• signal count std_logic_vector (3 downto 0)
  0000 misconception
• package, entity, architecture
• alias
• alias top std_logic_vector (1 downto 0) is
  count(3 downto 2)
• variable
• variable tmp bit
• process, function, procedure
• outside a process, a variable must be assigned
  to a signal

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Composite data - array

• type std_logic_vector is array (natural range ltgt)
  of std_logic
• signal a std_logic_vector (3 downto 0)
• type word is array (3 downto 0) of std_logic
• type table is array (0 to 3, 0 to 2) of bit
• constant exort table (
• 00_0,
• 01_1,
• 10_1,
• 11_0)

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Composite data - record

• type iocell is record
• a std_logic_vector (3 downto 0)
• e bit
• end record
• signal ra iocell
• ra.e lt 1

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Types and subtypes

• type word_size is integer range 0 to 15
• signal my_int word_size
• signal foo_int integer range 0 to 63
• if my_int foo_int then compile error
• subtype half_word is word_size range 0 to 3
• subtype semi_word is word_size range 12 to 15
• signal dubya half_word
• signal jay semi_word
• if dubya jay then NO compile error
• but this expression will always be false