Jai Henwood

1
Jai Henwood

• Introduction to VHDL
• ECE 5571
• 4/24/03
• Dr. Veton Këpuska

2
Goals and Objectives

• The goal of my project was to further my
  knowledge of VHDL
• Provide some history of the development of VHDL
• Introduce VHDL syntax and a few key concepts
  about VHDL.

3
Overview

• History of VHDL
• Go through a few example of VHDL
• - 8 bit shifter
• - 4 to 1 Mux
• - State machine

4
VHDL

• VHDL is an International IEEE Standard
  Specification Language (IEEE 078-2001) for
  Describing Digital Hardware Used by Industry
  Worldwide
• VHDL stands for VHSIC (Very High Speed Integrated
  Circuit) Hardware Description Language

5
History of VHDL

• In the 1970s the initial idea for a Hardware
  Description Language was discussed.
• But, the VHSIC program wasnt launched until
  1980.
• The goal was to create a common language that
  would shorten the time from concept to
  implementation for hardware design.

6
History of VHDL

• In July 1983 the contract was awarded to create
  VHDL by the Department of Defense
• - Intermetrics
• - IBM
• - Texas Instruments
• August 1985 Version 7.2 was released

7
History of VHDL

• It was first in December of 1987 that IEEE
  standardized VHDL 1076-1987
• VHDL also became an ANSI standard in 1988
• In September of 1993 VHDL was re-standardized to
  clarify and enhance the language

8
History of VHDL

• In 1998 a committee convened to update the
  VHDL-1993 standard.
• In 2001 IEEE revised the 1993 standard and the
  new standard today is 1076-2001

9
Other Languages besides VHDL

• On the way to standardizing VHDL other languages
  were devolved and some are still used
• AHPL A Hardware Programming Language
• CDL computer design Language
• CONLAN CONsensus LANguage

10
Other Languages besides VHDL

• IDL Interactive Design Language
• ISPS Instruction Set Processor Specification
• TEGAS Test Generation And Simulation
• TI-HDL TI Hardware Description Language
• Verilog Gateway Design Automation 1985
• ZEUS A HDL by GE cooperation

11
Basic VHDL Terms

• Entity - All designs are expressed in terms of
  entities. An entity is the most basic building
  block in a design. The uppermost level of the
  design is the top-level entity. If the design is
  hierarchical, then the top-level description will
  have lower-level descriptions contained in it.
  These lower-level descriptions will be
  lower-level entities contained in the top-level
  entity description.
• Architecture - All entities that can be simulated
  have an architecture description. The
  architecture describes the behavior of the
  entity. A single entity can have multiple
  architectures. One architecture might be
  behavioral, while another might be a structural
  description of the design.
• Configuration - A configuration statement is used
  to bind a component instance to an
  entity-architecture pair. A configuration can be
  considered as a parts list for a design. It
  describes which behavior to use for each entity,
  much like a parts list describes which part to
  use for each part in the design.

12
4 to 1 MUX
Inputs
Outputs
ABCD
Mux
Q
Sel
13
4 to 1 MUX

• library ieee
• use ieee.std_logic_1164.all
• -- 4 to 1 mux
• entity mymux is
• port (A, B, C, D in std_logic_vector(0 to 3)
• Sel in std_logic_vector ( 0 to 1
  )
• Q out std_logic_vector(0 to 3)
  )
• end mymux

• Library you need to include
• Comment
• entity name_of_entity is
• port(all your input and output signals)
• end name_of_entity

14
4 to 1 MUX

• mux4 is the name of my architecture
• Declaration of time as a constant
• begin the architecture
• Process mux_proc is initialized
• Variable temp is declared
• begin process mux_proc
• case on the Sel singal
• If anything else then temp is dont care
• If there was a delay on the mux
• end process
• end architecture

• architecture mux4 of mymux is
• constant delay time 100 ns
• begin
• mux_proc process ( A, B, C, D, Sel )
• variable temp std_logic_vector(0 to
  3)
• begin
• case Sel is
• when "00" gt temp A
• when "01" gt temp B
• when "10" gt temp C
• when "11" gt temp D
• when others gt temp
  "XXXX"
• end case
• Q lt temp after delay
• end process mux_proc
• end mux4

15
TestBench for 4 to 1 MUX

• library ieee
• use ieee.std_logic_1164.all
• entity mux_testbench is
• end mux_testbench
• architecture test of mux_testbench is
• signal A std_logic_vector(0 to 3)
• signal B std_logic_vector(0 to 3)
• signal C std_logic_vector(0 to 3)
• signal D std_logic_vector(0 to 3)
• signal Sel std_logic_vector(0 to 1)
• signal Q std_logic_vector(0 to 3)

• still have to begin with entity
• end the entity
• test is the name of the architecture
• the signals have to be the same as the port
  signals in your entity declaration of the program
  you want to test.

16
TestBench for 4 to 1 MUX

• This component declaration tells us that we have
  5 inputs A,B,C,D and Sel we also have one output
  Q
• The port map is used to link the signal A from
  your VHDL program to the signal A in your
  testbench
• Used incase you want to use different names

17
TestBench for 4 to 1 MUX

• test_process process
• begin Alt"1010" Blt"1011" Clt"1100" Dlt"1101"
  Sellt"00"
• wait for 500 ns Sellt"01"
• wait for 500 ns Sellt"10"
• wait for 500 ns Sellt"11"
• wait for 500 ns
• end process
• end test

• initialize your signal
• when Sel is 00 it should let A come through on Q
  with a delay of 100ns
• when Sel is 01 Q should be B
• end the process test_process
• end the test

18
8- Bit Shifter
Output
Input
clk
Shifter
load
rst
Q
8 bits
data
8 bits
19
8 Bit Shifter

• -- 8-Bit Shift Register
• library ieee
• use ieee.std_logic_1164.all
• entity shift is
• port (CLK, RST, LOAD in bit
• Data in bit_vector(0 to 7)
• Q out bit_vector(0 to 7))
• end rotate

• Comment
• Library you need to include
• entity name_of_entity is
• port(all your input and output signals)
• end name_of_entity

20
8 bit shifter

• architecture shifter1 of shift is
• begin
• reg process(RST, CLK)
• variable reg bit_vector(0 to 7)
• begin
• if(RST '1') then
• reg "00000000"
• elsif(CLK '1' and CLK'event) then
• if(LOAD '1') then reg Data
• . else
• reg reg(1 to 7) reg(0)
  
• end if
• end if
• Q lt reg
• end process
• end shifter1

• shifter1 is the name of my architecture
• shift is the name of my entity
• reg is the name of my process
• reg is also a local variable
• Begin the process reg
• if RST clear reg
• else wait for a clock event then
• reg Data if LOAD signal is high
• a bit shift
• R gets the value of reg
• end process
• end architecture

21
TestBench for 8 bit shifter

• still have to begin with entity
• end the entity
• test is the name of the architecture
• the signals have to be the same as the port
  signals in your entity declaration of the program
  you want to test.

• library ieee
• use ieee.std_logic_1164.all
• entity shift_testbench is
• end shift_testbench
• architecture test of shift_testbench is
• Signal CLK bit
• signal RST bit
• signal LOAD bit
• signal Data bit_vector(0 to 7)
• signal Q bit_vector(0 to 7)

22
TestBench for 8 bit Shifter

• component shift is
• port (CLK, RST, LOAD in bit
• Data in bit_vector(0 to 7)
• Q out bit_vector(0 to 7))
• end component
• begin
• test_shift shift port map(
• CLK gt CLK , RST gt RST,
  LOAD gt LOAD, Data gt Data,
• Q gt Q)

• port has all the input and output signals used in
  the VHDL program
• The port map is used to link the signal Data from
  your VHDL program to the signal Data in your
  testbench

23
TestBench for 8 bit Shifter

• creates a clock signal
• this is a 10 MHz clock
• end the process clock_gen
• this is only done once to set it off
• data is give a value
• every 400 ns Data is reset to 00000001
• end the process test_process
• end the test

• clock_gen process
• begin
• clk lt '0', '1' after 50 ns
• wait for 100 ns
• end process
• RSTlt'1', '0' after 200 ns
• test_process process
• begin
• Datalt"00000001"
• LOADlt'1', '0' after 400 ns wait
• end process
• end test

24
System Overview
DIP Switches
LED
Programmable Logic Device
An open switch will have a value of 1 and
closed switch value of 0
Strobe (pushbutton)
25
Functional Overview

• PLD monitors data stream looking for commands
• PLD responds to On command by turning LED On
• PLD responds to Off command by turning LED Off

On Off
AB 50
26
Details

• PLD receives 4 bits (one Hex digit) of data at a
  time
• Data is ready on rising edge of Strobe
• Output 1 to LED for ON / 0 for OFF

27
Programs Used

• To enter VHDL text nedit
• To compile ncvhdl made by Cadence
• To elaborate ncelab made by Cadence
• To simulate ncsim made by Cadence
• To create html and state diagrams
• visual_elite made by
  Innoveda

28
Why use VHDL

• Compared to schematic diagrams
• - More standardized portable
• - Easier to create
• - More concise
• - Easier to comment
• - Easier to read
• - Faster to simulate
• schematics/layouts can be automatically generated
  from VHDL by logic synthesis

29
Reasons for Modeling

• requirements specification
• documentation
• testing using simulation
• formal verification
• synthesis