VHDL for FPGA A Primer

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VHDL for FPGA --A Primer

• Kolin Paul / Sanjay Rajopadhye

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Designing for FPGAs

• This is for synthesis --- so put UR synthesis
  hats on ?
• U will build actual circuits .. Run them time
  them do exciting stuff ?
• Frustrations --- yes it is different from what
  programming in C is and for those from DSD
  class timing does play a real cool Part ..

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The Model

• Host-PCI card Model
• U build a coprocessor (addon accelerator)
• Overview of the Annapolis System

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Our Typical System
1M
1M
1M
Virtex 1000 1
Host
1M
1M
1M
LAD Bus
1 Virtex 1000 FPGA, 6 Memories (6 MB)
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So VHDL

• Simulation
• Defined in the LRM
• IEEE Standard is universally accepted
• Synthesis
• Specific to each vendor
• And this is what goes onto the chip (ASIC/FPGA)

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Hardware Description Language

• Hardware --- not software
• Description --- structure
• Language strong syntax and type declarations
• START with A BLOCK DIAGRAM

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VHDL Overview

• Programming Model
• Essentially CSP
• Combinational/Sequential
• Process is it always sequential ?
• Understanding how VHDL is converted into hardware
  gives us an insight how the synthesized circuit
  will look like

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Key Ideas

• Entity
• Architecture
• Port
• Process
• Signal and types
• Variable
• Conditionals
• Component and port map
• Generate
• Concurrency
• Sequential
• Sensitivity Lists

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An Example
Combinational
Sequential
Entity rsff is Port ( set,reset IN Bit
q,qb INOUT Bit) End rsff
Architecture sequential of rsff
is Begin Process(set,reset) Begin If set1 and
reset 0 then qlt0 after 2ns qb lt 1
after 4ns elseif set0 and reset 1
then qlt1 after 4ns qb lt 0 after
2ns elseif set0 and reset 0 then qlt1
after 2ns qb lt 1 after 2ns Endif End
process End first
Architecture netlist of rsff is Component nand2
port (a,b in bit c out bit) End
component Begin U1 port map
(set,qb,q) U2 port map (reset,q,qb) End
first
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Synthesis Example
Entity 3add is Port ( a,b,c std_logic
z out std_logic) End 3add
Architecture first of 3add is Begin zlt a and b
and c End first
Architecture second of 3add is Begin Process
(a,b,c) Variable tempstd_logic Begin temp b
and c z lt a and var End End second
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Synthesis Example

• A concurrent signal assignment that requires
  sequential hardware

Entity 3sel is Port ( a,b,c std_logic
z out std_logic) End 3sel
Architecture cond of 3add is Begin zlt a when
b1 else b when c1 else z End
first
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So The Application

• A systolic Multiplier to perform a Matrix Vector
  Multiply
• Simple application
• 3x3 matrix ? 3x1 vector
• Naïve code to get all of us on board
• The improvements are there for everyone to see
  and we shall solve them as class assignments

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So lets do the VHDL

• So what is the application .
• Design steps
• Please be modular in ur approach .. Makes
  debugging easier
• Also I prefer the bottom up approach in coding ..
  Top down while designing
• A simple uncomplicated design is the following

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The Algorithm

• Systolic .
• U have an idea of what that means
• Introduced by Kung and Leiserson
• I hope U have noticed the feed patterns and when
  the outputs are available
• So the Block diagram of the architecture would
  look like

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Well this could be a possible Implementation

• Sanjays Slide

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A Simple Implementation
Y AX
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So my Components are

• Shifter -- to feed in the data at the right time

• Systole -- essentially a multiply acc

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So my Components are

• The systolic multiplier -- performs the actual
  MVM

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The example codes

• Shifter
• Systole
• Multiplier

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Ok so this is the ckt

• And this is the compilation .
• Open vsim
• Make a project file saves u a lot in typing
• Make scripts .. Make modules .. Make libraries
  these are good coding practices

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Compile

• Compilation
• Please remember to check the VHDL93 option
• U can manually edit the mpf and the compile
  scripts (which are typically .do files)
• An introductory modelsim tutorial is in my home
  page (www.cs.colostate.edu/kolin and then follow
  the Misc link)

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How do We Simulate ..

• Force files nah too cumbersome definitely
  not elegant
• A small snippet of a force file

Force File force D 00101100               
-- force 8-bit variable D to 00101100    force
clk 0 0, 1 50 -r 100     -- means "force clk to 0
at 1ns, then to 1 at 50ns
-- and repeat every 100
ns.
-- This produces a clock with period  of
100ns -- and low time of 50ns.

• We will use a testbench to drive our architecture
• This is what a test bench looks like
• Testbench
• This is behavioral VHDL

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Simulation

• Simulation
• A small observation VHDL is not case sensitive
  .. Commands in modelsim are

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So my circuit simulates correctly

• Great the circuit simulates
• So now how do I get to the FPGA
• Key issues
• Remember the slide on where ur application will
  be wrt the board .
• And where will the data be .
• And clock

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The FPGA board stuff

• So now we need to simulate the entire thing .
• Remove the testbench that just showed that our
  application design is correct .
• We connect the appropiate inputs of the
  application to the VHDL model of the board
• Remember this is the portion that will not be
  synthesized it is already present we need to
  simulate it because our app needs data and
  control signals from these hardwired portions of
  the board

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StarFire Board (Simplified)
LAD Bus
1 Virtex 1000 FPGA, 6 Memories (6 MB)
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PE0
Right
Left
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Starfire Board
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Clocks 4 of them!?

• K, M, P, U
• KClock LAD Transactions (K?)
• MClock Memory Transactions
• PClock Processing Clock
• UClock User Clock
• Okay, but why? What are they?

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KClock LAD

• PE ?? Host
• 33MHz or 66MHz
• 33MHz Easy to Place and Route
• 66MHz 2X Host Bandwidth
• Host and Chip must agree!!
• Set in VHDL and Host Code
• Clock is actually based on PCI Clock
• Varies per host
• Ours is approx. 33.23MHz / 66.46MHz
• Asynchronous to all other clocks

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MClock Memory

• Speed of Memory IO
• Both Local Mezzanine
• User Selectable
• 25MHz 133MHz Wildstar
• 25MHz 100MHz Starfire

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Inside the Chips
. . . . .
. . . . .
. . . . .
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Register File

• Provides host access to 1-D array of 32-bit
  registers
• Size must be a power of 2
• Can be used for
• Ready The host says I can go now
• Done Hey Host, I am done!
• Small 32-bit IO The answer is 42!
• Run time parameters Threshold is 63

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ModelSim

• VHDL Simulation tool
• Annapolis provides
• Host simulation components
• VHDL Description of the WHOLE board
• LAD
• Memories (Local Mezzanine)
• Busses
• Etc
• You provide
• VHDL to run inside the chip (May contain
  Annapolis components as well)
• !Please Simulate .. Simulate simulate

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The Files

• So where do we add our application component .
• The Top Level File
• And how do we simulate .
• Here are the steps .
• Please make changes where it is indicated .. Do
  not experiment without understanding what you are
  doing ..

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Simulation .

• Now I suppose u realize why the Project file is
  so important .
• Simulate .
• Simulate until u are convinced that the
  application is behaving correctly
• The app_go and app_done signals are must .
• The host and the board depend on them ..

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So Synthesis

• Convinced that the simulation is Correct
• So now make changes in the makefile
• Makefile
• Type make .
• See .srr
• Remove all warnings that are in your component
  (if u can understand what the warning means and
  can account for it in the VHDL u can live with
  it ELSE U MUST REMOVE ALL WARNINGS THAT U DONT
  HAVE A CLUE ABOUT)

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Synplicity

• Synplicity Inc.
• Converts VHDL (or Verilog) into an EDIF
• EDIF description of your program in terms of
  virtex parts (4 input LUTs, FlipFlops, Ramblocks,
  Etc)
• Fast
• 1-30 minutes

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Place and Route

• Maps to lower level components
• Lays them out
• Routes between them
• Slow
• 10 minutes 2 days
• Provides a bitstream (.bit file)
• directly converted to .x86 for config

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Place and Route

• The makefile automatically does the place and
  route .
• Check the .par file to see that the timing
  constraints have been met .
• Else check critical paths
• Once satisfied, please use the estimated
  frequency in UR .c file and recompile .
• A .bit file ought to be produced

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Thats about it

• Logon to the specified machine
• ftp ur code .
• The executable corresponding to the .c file
• The .bit file
• The .dat files which contain ur data
• Run
• And enjoy .

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• Questions
• Tutorials Online on my Homepage
• Comments and suggestions
• kolin_at_cs.colostate..edu
• paulkolin_at_yahoo.com
• ....

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Issues to take care

• Data type
• Use std_logic_vector (makes interface simpler)
• Bit width --- (word size) I will use 16 bits
• How to I/O ? Major Q .. Will see later
• And what is the circuit going to look like