VHDL

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VHDL
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What is this presentation about?!

• This presentation will introduce the key concepts
  in VHDL and the
• important syntax required for most VHDL designs,

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Entity model interface

• The entity defines how a design element described
  in VHDL connects to other VHDL models
• and also defines the name of the model.
• It allows the definition of any parameters that
  are to be passed into the model using hierarchy.

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Entity definition

• entity test is
• .
• end entity test
• or
• entity test is
• end test

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Ports

• How to connect Entities together?
• -The method of connecting entities together is
  using PORTS.
• PORTS are defined in the entity using the
  following method
• port (
• ...list of port declarations...
• )

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Ports (Cont.)

• The port declaration defines the type of
  connection and direction where appropriate.
• port (
• in1, in2 in bit
• out1 out bit
• )

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Entity Port Modes

• in
• signal values are read-only
• out
• signal values are write-only
• buffer
• comparable to out
• signal values may be read
• inout
• bidirectional port

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Generics

• If the model has a parameter, then it is defined
  using generics.
• generic (
• gain integer 4
• time_delay time 10 ns
• )

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Constants

• It is also possible to include model specific
  constants in the entity using the standard
  declaration of constants method
• constant rpullup real 1000.0

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a complete examples, meet our first Entity.
test

• entity test is
• port (
• in1, in2 in bit
• out1 out bit
• )
• generic (
• gain integer 4
• time_delay time 10 ns
• )
• constant rpullup real 1000.0
• end entity test

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Architecture model behavior

• Implementation of the design
• Always connected with a specific entity
• one entity can have several architectures
• entity ports are available as signals within the
  architecture
• Contains concurrent statements

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Basic definition of an architecture

• While the entity describes the interface and
  parameter aspects of the model .
• the architecture defines the behavior.

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• VHDL allows different architectures to be defined
  for the same entity.
• architecture behaviour of test is
• ..architecture declarations
• begin
• ...architecture contents
• end behaviour

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Signals

• Signals are the primary objects describing the
  hardware system and are equivalent to wires.
• They represent communication channels among
  concurrent statements of system application.
• Signals can be declared in
• Package declaration
• Architecture
• Block
• Subprograms

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Hierarchical design

• Functions
• Packages
• Components
• Procedures

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Functions

• A simple way of encapsulating behavior in a model
  that can be reused in multiple architectures.
• Can be defined locally to an architecture or more
  commonly in a package

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• The simple form of a function is to define a
  header with the input and output variables as
  shown below
• function name (input declarations) return
  output_type is
• ... variable declarations
• begin
• ... function body
• end

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• function mult (a,b integer) return integer is
• begin
• return a b
• end

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Component
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(No Transcript)
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• library ieee
• use ieee.std_logic_1164.all
• -- here is the entity
• entity halfadd is
• port (a, b in std_logic
• sum, c out std_logic)
• end halfadd
• architecture comp of halfadd is
• begin
• -- a concurrent statement implementing the and
  gate
• c lt a and b
• -- a concurrent statement implementing the xor
  gate
• sum lt a xor b
• end comp

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• library ieee
• use ieee.std_logic_1164.all
• entity fulladd is
• port (ina, inb, inc in std_logic
• sumout, outc out std_logic)
• end fulladd
• architecture top of fulladd is
• component halfadd
• port (a, b in std_logic
• sum, c out std_logic)
• end component
• signal s1, s2, s3 std_logic
• begin
• -- a structural instantiation of two half adders
• h1 halfadd port map( a gt ina, b gt inb,
• sum gt s1, c gt s3)
• h2 halfadd port map( a gt s1, b gt inc,
• sum gt sumout, c gt s2)
• outc lt s2 or s3

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VHDL

• Case insensitive
• Comments '--' until end of line Statements are
  terminated by ''(may span multiple lines)
• List delimiter ','
• Signal assignment 'lt
• User defined names
• letters, numbers, underscores
• start with a letter

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VHDL . Identifier

• (Normal) Identifier Letters, numerals,
  underscores
• Case insensitive
• No two consecutive underscores
• Must begin with a letter
• Not a VHDL keyword

mySignal_23      -- normal identifierrdy, RDY,
Rdy    -- identical identifiersvector__vector  -
-  X special characterlast of Zout     --  X
white spacesidle__state      --  X consecutive
underscores24th_signal      --  X begins with
a numeralopen, register   --  X VHDL keywords
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Hierarchical Model Layout

• VHDL allows for a hierarchical model layout,
  which means that a module can be assembled out of
  several submodules. The connections between these
  submodules are defined within the architecture of
  a top module. As you can see, a fulladder can be
  built with the help of two halfadders (module1,
  module2) and an OR gate (module3).

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Component example
ENTITY half_adder IS PORT ( A, B
IN STD_LOGIC sum, carry OUT
STD_LOGIC ) END half_adder
ARCHITECTURE structural OF half_adder IS
COMPONENT xor2

PORT ( a, b IN STD_LOGIC c
OUT STD_LOGIC ) END COMPONENT COMPONENT
and2 PORT ( a, b
IN STD_LOGIC c OUT STD_LOGIC
) END COMPONENT BEGIN
ex1 xor2 PORT MAP ( a gt a, b gt
b, c gt sum ) or1 and2 PORT MAP ( a gt a, b
gt b, c gt carry )
END structural
begin     MODULE1 HALFADDER     port map(
A, B, W_SUM, W_CARRY1 )     MODULE2 HALFADDER
     port map ( W_SUM, CARRY_IN,                 
     SUM, W_CARRY2 )     MODULE3 ORGATE    
port map ( W_CARRY2, W_CARRY1, CARRY
) end STRUCT
entity FULLADDER is   port (A,B, CARRY_IN in   b
it           SUM, CARRY     out bit)end FULLA
DDERarchitecture STRUCT of FULLADDER is   signa
l W_SUM, W_CARRY1, W_CARRY2  bit    component
 HALFADDER      port (A, B                 in   
bit              SUM, CARRY  out bit)   
end component    component  ORGATE      port (A
, B  in   bit              RES  out bit)   
end componentbegin
begin    MODULE1 HALFADDER                    
 port map (  A           gt A,                   
                  SUM     gt W_SUM,              
                        B           gt B,        
                             CARRY gt W_CARRY1
)   . . .end STRUCT
ENTITY and2 IS PORT ( a, b
IN STD_LOGIC output OUT
STD_LOGIC ) END and2
ARCHITECTURE gate OF and2 IS BEGIN
output lt ( a AND b
) AFTER 5ns END gate
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Process

• The process in VHDL is the mechanism by which
  sequential statements can be executed in the
  correct sequence.
• Contains sequentially executed statements
• Exist within an architecture,
• Execution is controlled either via sensitivity
  list (contains trigger signals), or
  wait-statements

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Process
JustToShow process Begin Some statement
1 Some statement 2 Some statement 3 Some
statement 4 Some statement 5 end process
JustToShow

• JustToShow process
• Begin
• Some statement 1
• Some statement 2
• Some statement 3
• Some statement 4
• waitltconditiongt
• end process JustToShow

• Wait for type expression
• Wait until condition
• Wait on sensitivity list

Wait for 10ns
Wait until CLK1
Wait on Enable
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Process

• JustToShow process ( )
  
• Begin
• Some statement 1
• Some statement 2
• Some statement 3
• Some statement 4
• end process JustToShow

• VHDL provides a construct called sensenitivity
  list of a process
• The list specified next to the process keyword.
• The same as wait on sensitivity_list at the end
  of a process

JustToShow process
Begin Some statement 1 Some statement
2 Some statement 3 Some statement 4 wait
on end process JustToShow
SomeSig
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Process

• JustToShow process (signa1,signal2,signal3)
  
• Begin
• Some statement 1
• Some statement 2
• Some statement 3
• Some statement 4
• Some statement 5
• end process JustToShow

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Example
Signa1 0 Signal35
1
6
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Variables

• Variables are available within processes
• Named within process declarations
• Known only in this process
• Immediate assignment
• An assignment to a variable is made with
  symbol.
• The assignment take instance effect and each
  variable can be assigned new values as many times
  as needed.
• A variable declaration look similar to a signal
  declaration and starts with variable keyword
• Keep the last value
• Possible assignments
• Signal to variable
• Variable to signal
• Types have to match

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Variables vs. Signals

• Signals
• In a process, only the last signal assignment is
  carried out
• Assigned when the process execution is suspended
• lt to indicate signal assignment
• Variables
• Assigned immediately
• The last value is kept
• to indicate variable assignment

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Variables vs. Signals (contd.)
A
C

X

X
B
B
C
C

Y

Y
B
B
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Variables

• process(C,D)
• Variable Av,Bv,Ev integer 0
• begin
• Alt2
• BvltAvC
• AvltD1
• Ev lt Av2
• A ltAv
• B ltBv
• E ltEv
• end process