VHDL AES 128 Encryption/Decryption

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VHDL AES 128 Encryption/Decryption
Bradley University Department of Electrical and
Computer Engineering
Senior Capstone Project
Advisor Dr. Vinod Prasad
David Leifker Gentre Graham
April 7th 2005
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Presentation Outline

• Project Introduction
• Functional Description
• Difficulties Solutions
• Simulation, Verification, Demonstration
• Conclusion

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Project Introduction AES

• AES (Advanced Encryption Standard)
• Key Lengths 128,192,256 bits (FIPS 197)
• Block Cipher
• Approved by NSA (National Security Agency)
• Plain Text
• Unencrypted Data
• Cipher Text
• Encrypted Data
• Encryption Key (Secret Key)
• Enables conversion between Cipher Text Plain
  Text

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Project Introduction

• VHDL (Very High Speed Integrated Circuit Hardware
  Description Language)
• FPGA (Field-Programmable Gate Array)
• HID ( Human Interface Device)
• PS/2 Keyboard
• LCD ( Liquid Crystal Display )

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Project Introduction Applications

• Secure Communication
• ATM
• DVD Content
• Secure Networks
• Secure Storage
• Confidential Corporate Documents
• Government Documents
• FBI Files
• Personal Storage Devices
• Person Information Protection

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Project Introduction Hardware

• PC with Xilinx ISE 6.31i
• NU Horizons
• Xilinx Spartan III Development Board
• XCS400-4 PQ208C
• PS/2 Input
• 4 x 20 Line LCD Display

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Presentation Outline

• Project Introduction
• Functional Description
• Difficulties Solutions
• Simulation, Verification, Demonstration
• Conclusion

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Functional Description
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Sub-System Block Diagram
Program Control Logic
PS2 Keyboard Interface
AES Core
719 LoC
180 LoC
RAM
51 LoC
LCD Interface
1254 LoC
ROM
Misc. LoC 290
440 LoC
67 LoC
Total Lines of Code 3000
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Sub-System Block Diagram
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Inside The AES Core
Encryption
Key Expansion
Decryption
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Inside The AES Core
Key Schedule
Current State
Next State
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Inside The AES Core
Current State
Next State
256 Byte Array
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Inside The AES Core
Next State
Current State
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Inside The AES Core
Current State
Next State
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Inside The AES Core
Next State
Current State
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Presentation Outline

• Project Introduction
• Functional Description
• Difficulties Solutions
• Simulation, Verification, Demonstration
• Conclusion

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Difficulties Solutions

• Development Board PS/2 Port
• Replaced with External PS/2 Port
• Development Board Documentation Did Not Reflect
  Board Specifications
• Clock Speed
• LCD Character Addressing (4x24 vs 4x20)
• LCD Timing
• Test Bench Development
• Area Constraints of the FPGA
• Hard Coded Encryption Key
• Reduction of States by Looping (LCD)

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Presentation Outline

• Simulation, Verification, Demonstration
• FIPS 197 Documented Example
• ModelSim Computer Simulation
• FPGA Demonstration

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Demonstration FIPS 197
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Demonstration Encryption
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Demonstration Decryption
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Demonstration Encryption
ModelSim Computer Simulation
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Demonstration Decryption
ModelSim Computer Simulation
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Software Flow Chart
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Demonstration Splash Screen
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Demonstration ASCII Input
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Demonstration ASCII Input
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Demonstration ASCII Input
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Demonstration HEX Input
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Demonstration Encryption
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Demonstration Decryption
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Improvements Additions

• Larger LCD Display
• 192 or 256 Bit level Encryption
• High Speed Mode
• PC Integration

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Questions?