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VHDL????

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Title: VHDL Author: gary Last modified by: gary Created Date: 4/10/2005 4:59:45 PM Document presentation format: Company – PowerPoint PPT presentation

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Title: VHDL????


1
VHDL????
  • ??4_10???
  • ?????
  • ??B09322001

2
??
  • ???BCD?????????LED??09?????

3
???
4
  • ?I(3,)I(2),I(1),I(0)??? 0 0 0 0 ,
    ???O(0)O(9)? 1000000000
  • ?I(3,)I(2),I(1),I(0)??? 0 0 0 1 ,
    ???O(0)O(9)? 0100000000
  • ?I(3,)I(2),I(1),I(0)??? 0 0 1 0 ,
    ???O(0)O(9)? 0010000000
  • ?I(3,)I(2),I(1),I(0)??? 0 0 1 1 ,
    ???O(0)O(9)? 0001000000
  • ?I(3,)I(2),I(1),I(0)??? 0 1 0 0 ,
    ???O(0)O(9)? 0000100000
  • ?I(3,)I(2),I(1),I(0)??? 0 1 0 1 ,
    ???O(0)O(9)? 0000010000
  • ?I(3,)I(2),I(1),I(0)??? 0 1 1 0 ,
    ???O(0)O(9)? 0000001000
  • ?I(3,)I(2),I(1),I(0)??? 0 1 1 1 ,
    ???O(0)O(9)? 0000000100
  • ?I(3,)I(2),I(1),I(0)??? 1 0 0 0 ,
    ???O(0)O(9)? 0000000010
  • ?I(3,)I(2),I(1),I(0)??? 1 0 0 1 ,
    ???O(0)O(9)? 0000000001

5
??VHDL???
  • Library ieee -- ??ieee???
  • use ieee.std_logic_1164.all -- ??ieee??????
  • entity Decoder4_10 is -- ??IC??
  • port(
  • I in std_logic_vector(3 downto 0)
  • O out
    std_logic_vector(9 downto 0))
  • End
  • architecture main of Decoder4_10 is -- ??????
  • begin
  • process(I) -- ????I
  • begin
  • if I"0000" then Olt"0000000001"
  • elsif I"0001" then Olt"0000000010"
  • elsif I"0010" then Olt"0000000100"
  • elsif I"0011" then Olt"0000001000"
  • elsif I"0100" then Olt"0000010000"
  • elsif I"0101" then Olt"0000100000"
  • elsif I"0110" then Olt"0001000000"
  • elsif I"0111" then Olt"0010000000"

6
LATTICE??
? ?? ??? Lattice Semiconductor ????
7
????Project
????
??VHDL??
8
1.????????(Device)
2.?ispLSI2032E
3.OK???
9
1.???????Source
3.OK
2.??VHDL Module??
10
1.????Decoder4_10
4.OK
2.????
3.????
11
???????
12
???????????
13
????
14
???? ???????
15
1.??Download Cable
2.????????????
16
Synplify???
???Project
??Project
17
? NEW HDL File
????????
18
1.????
2.????
3.??
4.OK
19
?????
???
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