VHDL? ????? ??

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VHDL? ????? ??

• ????? ?????
• ? ? ?

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? ?

• Agenda
• ASIC Design
• VHDL ? ?? ?? ?? ??
• VHDL ? ASIC ?? ???? ??
• VHDL ???, ?? ? FPGA ?? ?
• VHDL ?? ?? ? ?? ??

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Agenda

• Mobile Society Change
• PC -gt Mobile Communication
• Component -gt System
• Design Methodology
• ASIC Design Flow
• SoC Design Flow

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Shift 1 From PC to Communications Centric
Services
Broadband Network
100Mb/sWLAN
RF
20Gop/s
Java Configurable Multi-Standard Info Plug...
lt1 Watt
WWW
LAN
MPEG 4-7 100 Gop/s 5 Gtr/s 10 Watt
??
-gt Domain Specific Computing
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Shift 2 Chip from Component -gt System
Services
Network
embedded C
RF
System on
asp
opamp
Filters AD/DA
dspP
IC
ASIP
memory
µP
µC
gate
RT-ops
ASIC
FSM
FPGA
Silicon Board
VHDL
OO cC
Software
Hardware
Design Software
t
1960
70
80
90
2000
2010
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Mobile Society? ?? ??

• PC ??? ??
• 1980?? ??? ?? 8-bit/64K Memory PC ??? ??
• Internet ??? ??
• PC ??, E-mail (WS, PC), WWW ??? ??
• Mobile Phone ??? ??
• 1995? ??? ? Analog Mobile Phone, Digital Phone
  ??? ??
• 3?? IMT-2000 -gt ???? ?? ??
• Post PC ??? ??
• ??? ??? ??? ??? ???? ? Post PC
• Network Information Appliance(??????) ??

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Post-PC Silicon System in 2010
40nm , 1G Transistors
www gps
RF / Analog
Embedded Software
100 MByte Distributed Memory
32 Bit ASPPs
Speech Pen Vision Bio Motion Security Sensors
gt1GHz
Re-configurable Interconnect
lt1 Watt
Display Sound Data Bio Actuators
10 M gate Re-configurable Computing
10 M Gate Hardwired Logic
lt1 Volt
50 GIPS-500GOPS

FLEXIBILITY - REUSE - IP
ENERGY/OP 100
More than IP assembly!!
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Key Enabling Technologies
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Productivity Gap in Hardware Design

Source sematech97
A growing gap between design complexity and
design productivity
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Increasing Designer Productivity

• 7 Areas
• A Register-transfer level to layout B Low
  power C Libraries
• D Analog/mixed-signal design E Intellectual
  property reuse
• F Hardware/software coverification G
  System-level specification

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1. ASIC Design The Silicon Evolution

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ASIC Design - Technology Diffusion
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ASIC Design - Profit Loss
Source McKinsey
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ASIC Design-VLSI Crisis

• feature size - decreases by a factor of 2 in
  every 4 years.
• chip size - increases
• 5 mm 1977, 15-20 mm in 2000, 25-30 mm in 2010
• total transistor count rises by a factor of 2 in
  every 18 months.
• fabrication cost - doubles for each generation
• programmer productivity
• 30 lines/day (20/line) 0.5 lines/day
• designer productivity
• 30 transistors/day
• 30 HDL lines/day, 300 gates/day, 1200
  transistors/day

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ASIC Design-VLSI Crisis

• HDL based design
• simulation
• logic synthesis
• behavioral synthesis
• Formal verification
• Equivalence verification of HDL based designs of
  different abstract levels.
• Intellectual Property
• vendor library
• synthesizable core

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ASIC Design-Design Reuse

• More than 100M gates in 40 nm
• 10 1M gates per synthesis module
• 20 - 100 synthesis modules per chip
• behavioral synthesis
• 100M gates by the years 2010
• Design Reuse
• constant project team sizes
• shrinking project completion times
• Large portions of the chip will result from
  reusing existing blocks.

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ASIC Design-System Design

• Building blocks
• image/video processing
• speech codec
• communications
• ASIC Design
• becomes a system integration
• system level analysis of available building
  blocks
• Balancing of available IP building blocks
• product differentiation at the system level

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ASIC Design-Intellectual Property

• IP Development / Integration House
• Diverse market needs
• e.g.gt graphics chips with digital modem
  capability
• ASIC Design
• becomes a system integration
• performance analysis of availiable building
  blocks
• balancing of available building blocks
• Reusing IP Building Blocks
• only viable approach to designing over 1M gates
  reasonable time.
• Reusing IP building blocks developed outside is
  the way to merge knowledge from different
  applications onto a single chip

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ASIC Design-Intellectual Property

• On Silicon IP(hard IP)
• ASICs
• chip sets
• programmable DSPs
• Off Sillicon IP(soft IP)
• synthesizable core
• a reference implementation in sillicon
• adds a credibility
• Firm IP(soft IP)
• RTL level libraries

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ASIC Design-Levels of Abstraction

• Architectual /Algorithmic
• described in terms of the algorithms the system
  performs.
• High lebel design tradeoffs, e.g. hardware
  /software codesign.
• RTL
• flow of data and control signals whthin / between
  functional blocks.
• schedules assignments at clock edges.
• Gate
• interconnection of switching elements (gates).
• Switch
• describes logic behavior of transistor circuits.
• Evaluates conflicts caused by signal strengths of
  multiple nets.

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Market Pressures

• Size of Custommer Telecom Market lt US 2T
• Products
• Signal-Dominated HW Systems Under SW Control
• Protable, Low-Power, Manufacturable, Time to
  Market
• Average Lifetime of a Consumer Product 6-18 mos.
• Success Depends Critically on the Ability to
  Design these Systems FAST!

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When Does One Use Behavioral Synthesis

• Use behavioral synthesis when
• Algorithmic description exists
• Complex data flow and/or memory access
• Operations can be moved
• Designs specification still changing
• Need to explore architecture, pipelining, etc.

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Behavioral Synthesis
CYC OP 1 2 3 4
HARDWARE ALLOCATION
SCHEDULING

• Looks at high-level constraints
• Latency, Throughput, Clockperiod goals
• Extracts control /data flow behavior (Scheduling)
• Assigns operations to resources and states
• Assigns variables to storage elements
  (Allocation)
• optimization of storage
• decides if temporary storage necessary
• FSM generated automatically
• defines state /state transitions
• cycle /cycle implementation of behavior

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Behavioral Synthesis Definition
input
FOR I in 0 TO 2 LOOP WAIT until clkevent and clk
1 IF (rgbi lt 248) THEN p rgbi mod 8
q filter(x,y)8 END IF ...
m
o
m
R
input
output
clk
Enable
Instructions Operations Variables Arrays signals c
onstraints
Scheduling Allocation Loop pipelining Chaining Mul
ti cycle operations Memory management Reset
style Clocking sytyle
Functional units Registers Memories Multiplexers D
W components
Collection of techniques for sequential
optimization
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?? ???(design automation) ? ??? ??? ?? -
?? ??, ?? ??, GUI? ?? ?? ? ???? ?? ??? ??
- ?? ??? ??, ?? ??? ?? ? ???? ?? ? ??? ????
??? ?????? ??
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HDL ??? ??? ?????? ??
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??(synthesis)?? ? ? ??? HDL? ??? ???? ??
??? ?? ? ?? ?? ???
(translation) (optimization) ? ??
??? ?? RTL ?? (HDL ??) ??? ??
(??? ?? ??) ? ??? ??? ???, ??? ???
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2. VHDL ? ?? ?? ?? ??

• ASIC ??
• ?? ??(?? ????)
• VHDL
• ? VHDL ??? ?????
• VHDL ??? ? ? ??
• VHDL ??? ??

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ASIC ??(1)
IC ?? ?? ??
ASIC (Application Specific IC) ??
?? ?? ?? ??
-???( semi-custom ) ??? -?? ( application
specific ) -?? ?? ?? ( shorter design turnaround
time (DAT) )
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ASIC ??(2)
- gate density ?? - ??(??) ?? - ?? ??
?? ??? ??? mask pattern ? ??
full-custom IC
semi-custom IC
ASIP (co-design)
ASIC
- Gate Array - Standard Cell - PLA, PAL
- FPGA(Field Programmable GA) - PLD(Programmable
Logic Device)
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?? ??(logic synthesis)
schematic based design process
language based design process
circuit design with HDL(Hardware Description
Language)
circuit design with schematic editor
logic synthesis
simulation
simulation
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VHDL(Very High Speed IC HDL)

• - 1981. HDL workshop
• ??? HDL ?? ??? ??
• - ????, Department of Defense Requirements
• for HDL ?? ??
• - 1984. VHDL version 7.2 ??(? ??? ??)
• - 1986. 2? VHDL ?? ??( ???? ???)
• 1987. IEEE Standard 1076-1987 VHDL ??
• 1993. VHDL 1076-1993 VHDL ???? ??

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? VHDL ??? ?????
??? ??? ?? ?? ???? ????.
??? ?? ????
circuit design with HDL
?? ?? ?? ??.
?? ??
logic synthesis
?? ?? ???? ?? ??
netlist ?? ??. DAT ??
simulation
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VHDL??? ??
? ?? ??? ?? - ?? ?? ?? ??? ?? ? ??? ?(quality)
?? - ?? ?? ?? ???? ??? ?? ? vendor ? ?? ???
?? ? ?? ?? ?? - ?? ??? ( design re-usability
) ? ?? ?? ?? - ????? ??? structured design
?? ?? ? ??? ??(IFIP 172) ? ??
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VHDL??? ??
? ??? ?? - ??? ??? ?? ???? - ??? ??
??? ? ?? ? ?? ?? ?? ? ?? - ?? ?? ??, ??
??? ?? ??? ???? ???. - ?? ?? ?? ( propagation
delay ) ??? ???.
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VHDL??? ??
? VHDL ? ??(??)? ??, ?? ??? ??? ?? ??? ????
??? ??(?) ?. A B x C ? VHDL ? ????? ???
???. ? H/W ?? ??? ??? ??? ???. ? ?? ?? ??? ??
????.
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2. VHDL ? ASIC ?????? ??

• ?? ??? ?? ? ?? ?? ??
• ?? ?? ??(design hierarchy)
• ASIC ?? ????
• VHDL ?? ???? ??? ?

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?? ??? ??
? ??? ?? ?? - primitive logic gates,
decoder, multiplexer - adder, subtractor ,
comparator, multiplier ? ? ?? ?? ?? ? ???
? ???? ??? ?? - up/down counter, timing
generator, event counter ? ? ????? ?? ??
- register, latch, shift register,
accumulator ? ? ?? ?? ?? -
sequencer, controller, finite state machine ?
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?? ?? ??
? VHDL ? ?????? ?? ??? ????? ???. ? ??? ???
?? ?? VHDL ? coding ??. ? ?? ????? ?? ??(timing
delay) ??? ??? ?????? ???.
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abstract design
?? ?? ??
detailed design
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ASIC ?? ????
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ASIC ?? ????(1)
? ??? ?? ?? ? ?? ?? - ???? ? ? ?? ?? - ??
??? H/W ? S/W ?? ??? ?? - ?? ?? module ? ??
?? ? ?? ????? ? ?? specification ?? - ????
H/W ??? ?? - VHDL ?? ?? ( ?? ) ? ?? ?? ( ??
) - gate count ?? ? ??? ?? ?? ??
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? ?? ?? block diagram
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? ?? ??? A? block diagram
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ASIC ?? ????(2)
? ??? ? ????? ?? - controllability ?
observability ?? ? ??(yield) ?? - ??? ?? ??
?? (? 24-bit counter, ) ? ?? ?? ??
- ?? (??) ?? ?? ? ??? ( macro ) ? ?? - ?
?? ? ?? ?? VHDL ?? ? ????? ??? ?? ??
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?? ?? ?? ?? ??
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ASIC ?? ????(3)
? ????? ( simulation ) - ?? VHDL ?? compile ?
link ? debugging - ??/?? ????? ?? ??
( ? half-adder ? AND gate ) ? ?? ??
- ASIC ?? ?? ??( ?? component ????? ?? ) - ??
??? ? ?? ??? ? ASIC ??(??, verification) -
physical layout ?? gate ?? ?? ?? ?? ?? - I/O
pin assignment, ERC ( Electrical Rule Checking )
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VHDL ???? ??? ?
? VHDL ? coding ?? ?? ?? ?? ?????? logical
structure ? ?? ???? ?? ???? ??. ? VHDL ??? ??
gate-level ASIC ??? ???? ???? ?? ??? ???
??(test pattern)? ???? ????.
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3. VHDL ???, ?? ? FPGA ?? ?

• ??? ?? VHDL ???
• VHDL ???? ????? ? ?? ?? ?
• VHDL ???? FPGA ??
• ?? ??? ? ?? ??? ??

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??? ?? VHDL ???
? ??? ?? ?? ??? (Behavioral Descriptions) ?
???? ??(Register Transfer) ?? ??? (??? ??
(Dataflow Descriptions) ???) ? ??? ?? ???
(Structural Descriptions)
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??? ?? ?? ??? (Behavioral Descriptions)
architecture behavioral of eqcomp4
is begin comp process (a, b ) begin if a b
then equals lt 1 else equals lt
0 end if end process comp end
behavioral
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???? ??(RT) ?? ??? (Data-flow Descriptions)
architecture dataflow of eqcomp4 is begin
equals lt 1 when (a b) else 0 --
equals is active high end dataflow
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??? ?? ??? (Structural Descriptions)
architecture structural of eqcomp4 is signal
x std_logic_vector (0 to 3) begin u0 xnor2
port map (a(0), b(0), x(0)) u1 xnor2 port map
(a(1), b(1), x(1)) u2 xnor2 port map (a(2),
b(2), x(2)) u3 xnor2 port map (a(3), b(3),
x(3)) u4 and4 port map (x(0), x(1), x(2),
x(3), equals) end structural
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???? VHDL ??? ?
? 1-bit half-adder(HA) VHDL ??? - Data-flow
Descriptions - Behavioral Descriptions ?
1-bit full-adder(FA) VHDL ??? - Structural
Descriptions(2 HA OR gate) - Behavioral
Descriptions
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half adder (1) entity ???
entity half_adder is port ( a, b in bit
sum, carry out bit ) end half_adder
a
sum
half adder
carry
b
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?? 1 half adder(2)(architecture body) (Register
Transfer Level Modeling)
architecture RTL_description of half_adder
is begin process begin sum lt a xor b
carry lt a and b wait on a, b end
process end RTL_description
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?? 2 half adder(3) (architecture
body) (Behavioral Modeling)
architecture behav_description of half_adder
is begin process begin if (a b) then
sum lt '0' else sum lt '1' end if
if (a '0') or (b '0') then carry lt
'0' else carry lt '1' end if wait
on a, b end process end behav_description
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?? 1 ? ?? 2? VHDL ?? ?? (???, ?? ?? ?? ??, ????
???)
Design Equations carry a b sum
a /b /a b Worst Case Path tPD 8.5 ns
for the path (a ? sum, a ? carry ) Utilization
(using Package CY7C371-143JC) Total PIN
signals 4/38 Macro-cells Used 2/32 Unique
Product Terms 3/160
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????? ??(half adder)
?????? (propagation delay)
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full adder(1) entity ???
entity full_adder is port ( x, y, c_in
in bit s_out, c_out out bit ) end
full_adder
x
s_out
y
full adder
c_out
c_in
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full adder(2) architecture body
architecture structure of full_adder is
signal temp_sum, temp_carry_1, temp_carry_2
bit component half_adder port ( a, b in
bit sum, carry out bit ) end component
component or2 port ( i1, i2 in bit o
out bit ) end component begin port map
( ) ... end structure
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full adder(3) block diagram
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full adder(4) structural descriptions
u0 half_adder port map ( a gt x, b gt y,
sum gt temp_sum, carry gt temp_carry_1) u1
half_adder port map ( a gt temp_sum, b gt c_in,
sum gt s_out, carry gt temp_carry_2 ) u2
or2 port map ( i1 gt temp_carry_1, i2 gt
temp_carry_2, o gt c_out )
x
temp_sum
a
sum
U0
y
Temp_carry_1
carry
b
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full adder(5) ?? ?? ??
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full adder(6) Behavioral Modeling
architecture behav_description of full_adder
is begin process variable I integer if
(x 1) then I lt I 1 end if if (y
1) then I lt I 1 end if if (c_in
1) then I lt I 1 end if if (I 1)
or (I 3) then s_out lt 1 else s_out
lt 0 end if if (I gt 1) then c_out lt
1 else c_out lt 0 end if wait on x,
y, c_in end process end
behav_description
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full adder(7) ?? ?? ??
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VHDL ???? FPGA ??
? Standard Cell - ??? ?? ??? ?? ?? ? Gate
Arrays - metal layer ? ??? ?? ?? ??? ?? ?
PLD(Programmable Logic Devices) - 2-stage
arrays AND plane OR plane -
PROM(Programmable ROM), PLA, PAL ? FPGA(Field
Programmable Gate Arrays) - PLD ? ?? ?? ??
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FPGA
logic cell
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VHDL ???
???? ??
? ? ? ?
?? ????
netlist ?? ?? ???
?? ? ?? ????
?? ?? (??? ?? ?? ?)
???? ????? ?? (JEDEC ??)
??? ??
???? ?? ????? ?? (VHDL ?? ?? ??)
????? ???? ( VHDL ????? )
??? ??
??? ??
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Device ??
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VHDL ?? ??(compilation)
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CPLD ?? ?(1)
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CPLD ?? ?(2) - ? ??? ??
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??? timing ?? ??
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?? ?? ?? ??
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?? ??? ? ?? ???
?? ?? gate density ?
area minimization
?? ?? ?? ??(critical path)?? ?? ?
performance optimization
?? ?? ???? ?? ??? ASIC ? ??
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? ?? ??
Sum lt BusABusBBusCBusD
Sum lt (BusABusB)(BusCBusD)
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? ?? ??(resource sharing)(1)
Y lt A B When Sel 1 Else Y lt C D
Which one to choose?
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? ?? ??(resource sharing)(2)
Y lt A B When Sel 1 Else Y lt C D
?. ? ?? ?????? ? ?? ??? MPX1 lt A When Sel
1 Else C MPX2 lt B When Sel 1 Else D Y
lt MPX1 MPX2 ?. ? ?? ???? ? ?? ????? Sum1 lt
A B Sum2 lt C D Y lt Sum1 When Sel 1
Else Sum2
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? ?? ??? ???(1)
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? ?? ??? ???(2)
C lt A or (B and not (Select)) ??? Z lt A when
Select 0 else C
Z lt A
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? ?? ???(1)
?? ?? (critical speed) ?? ???
SigA lt 1 When Count 1101000011001010 Else
0
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? ?? ???(2)
And/Or ??? ??
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? ?? ???(3)
A ?? Z ??? ?? ?? ???
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?? ??? ? ?? ??? ? ??? ?
RESULT lt A B
? ??? ?? ?? ?? - design requirement? ?? ???
tradeoff ? component library?? ?? ??? ???? ??
- ?? ?? ?? ?? - technology dependent ?
carry lookahead ?? ?? (?? VHDL? coding) - ???
?? 2.5 ? 50 ??
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VHDL ?? ??(1)

• ??(integration)
• ?? ??? ??? ?? ??? ??.
• ? gate delay
• ASIC ?? ?? ?? ??? ??? ??.
• ?? ??? ???
• ?? ??? entity ? ?? ??.
• VHDL ?? ??? ?? ??? ?? ??.

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VHDL ?? ??(2)

• ??? ?? ???
• ?? ??( formal verification )
• ??? ?? ??
• DSP( Digital Signal Processing ) Application
• bus-style/pipelined processor
• register/register file synthesis